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[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on D76591 It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name? Differential Revision: https://reviews.llvm.org/D92147
1 parent ca28883 commit ad923ed

24 files changed

+252
-169
lines changed

‎lld/test/ELF/riscv-branch.s

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5,17 +5,21 @@
55

66
# RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32
77
# RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
8-
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
9-
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
10-
# CHECK: 63 02 00 00 beqz zero, 4
11-
# CHECK: e3 1e 00 fe bnez zero, -4
8+
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32
9+
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64
10+
# CHECK-32: 63 02 00 00 beqz zero, 0x110b8
11+
# CHECK-32: e3 1e 00 fe bnez zero, 0x110b4
12+
# CHECK-64: 63 02 00 00 beqz zero, 0x11124
13+
# CHECK-64: e3 1e 00 fe bnez zero, 0x11120
1214
#
1315
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv32.limits
1416
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv64.limits
15-
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
16-
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
17-
# LIMITS: e3 0f 00 7e beqz zero, 4094
18-
# LIMITS-NEXT: 63 10 00 80 bnez zero, -4096
17+
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s
18+
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s
19+
# LIMITS-32: e3 0f 00 7e beqz zero, 0x120b2
20+
# LIMITS-32-NEXT: 63 10 00 80 bnez zero, 0x100b8
21+
# LIMITS-64: e3 0f 00 7e beqz zero, 0x1211e
22+
# LIMITS-64-NEXT: 63 10 00 80 bnez zero, 0x10124
1923

2024
# RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
2125
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s

‎lld/test/ELF/riscv-jal.s

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5,17 +5,21 @@
55

66
# RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32
77
# RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
8-
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
9-
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
10-
# CHECK: 6f 00 40 00 j 4
11-
# CHECK: ef f0 df ff jal -4
8+
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32
9+
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64
10+
# CHECK-32: 6f 00 40 00 j 0x110b8
11+
# CHECK-32: ef f0 df ff jal 0x110b4
12+
# CHECK-64: 6f 00 40 00 j 0x11124
13+
# CHECK-64: ef f0 df ff jal 0x11120
1214

1315
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv32.limits
1416
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv64.limits
15-
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
16-
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
17-
# LIMITS: 6f f0 ff 7f j 1048574
18-
# LIMITS-NEXT: ef 00 00 80 jal -1048576
17+
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s
18+
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s
19+
# LIMITS-32: 6f f0 ff 7f j 0x1110b2
20+
# LIMITS-32-NEXT: ef 00 00 80 jal 0xfff110b8
21+
# LIMITS-64: 6f f0 ff 7f j 0x11111e
22+
# LIMITS-64-NEXT: ef 00 00 80 jal 0xfffffffffff11124
1923

2024
# RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
2125
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s

‎lld/test/ELF/riscv-undefined-weak.s

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,15 +52,14 @@ relative:
5252
# PC-LABEL: <branch>:
5353
# PC-NEXT: auipc ra, 1048559
5454
# PC-NEXT: jalr -368(ra)
55-
## FIXME: llvm-objdump -d should print the address, instead of the offset.
56-
# PC-NEXT: j -70008
55+
# PC-NEXT: j 0x0
5756

5857
## If .dynsym exists, an undefined weak symbol is preemptible.
5958
## We create a PLT entry and redirect the reference to it.
6059
# PLT-LABEL: <branch>:
6160
# PLT-NEXT: auipc ra, 0
6261
# PLT-NEXT: jalr 56(ra)
63-
# PLT-NEXT: j -70448
62+
# PLT-NEXT: j 0x0
6463
branch:
6564
call target
6665
jal x0, target

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,24 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
102102
MO.getExpr()->print(O, &MAI);
103103
}
104104

105+
void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
106+
unsigned OpNo,
107+
const MCSubtargetInfo &STI,
108+
raw_ostream &O) {
109+
const MCOperand &MO = MI->getOperand(OpNo);
110+
if (!MO.isImm())
111+
return printOperand(MI, OpNo, STI, O);
112+
113+
if (PrintBranchImmAsAddress) {
114+
uint64_t Target = Address + MO.getImm();
115+
if (!STI.hasFeature(RISCV::Feature64Bit))
116+
Target &= 0xffffffff;
117+
O << formatHex(Target);
118+
} else {
119+
O << MO.getImm();
120+
}
121+
}
122+
105123
void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
106124
const MCSubtargetInfo &STI,
107125
raw_ostream &O) {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,8 @@ class RISCVInstPrinter : public MCInstPrinter {
3232

3333
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
3434
raw_ostream &O, const char *Modifier = nullptr);
35+
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
36+
const MCSubtargetInfo &STI, raw_ostream &O);
3537
void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
3638
const MCSubtargetInfo &STI, raw_ostream &O);
3739
void printFenceArg(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -604,15 +604,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
604604
case RISCVOp::OPERAND_SIMM12:
605605
Ok = isInt<12>(Imm);
606606
break;
607-
case RISCVOp::OPERAND_SIMM13_LSB0:
608-
Ok = isShiftedInt<12, 1>(Imm);
609-
break;
610607
case RISCVOp::OPERAND_UIMM20:
611608
Ok = isUInt<20>(Imm);
612609
break;
613-
case RISCVOp::OPERAND_SIMM21_LSB0:
614-
Ok = isShiftedInt<20, 1>(Imm);
615-
break;
616610
case RISCVOp::OPERAND_UIMMLOG2XLEN:
617611
if (STI.getTargetTriple().isArch64Bit())
618612
Ok = isUInt<6>(Imm);

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -160,6 +160,7 @@ def simm12_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
160160
// A 13-bit signed immediate where the least significant bit is zero.
161161
def simm13_lsb0 : Operand<OtherVT> {
162162
let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
163+
let PrintMethod = "printBranchOperand";
163164
let EncoderMethod = "getImmOpValueAsr1";
164165
let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
165166
let MCOperandPredicate = [{
@@ -168,8 +169,7 @@ def simm13_lsb0 : Operand<OtherVT> {
168169
return isShiftedInt<12, 1>(Imm);
169170
return MCOp.isBareSymbolRef();
170171
}];
171-
let OperandType = "OPERAND_SIMM13_LSB0";
172-
let OperandNamespace = "RISCVOp";
172+
let OperandType = "OPERAND_PCREL";
173173
}
174174

175175
class UImm20Operand : Operand<XLenVT> {
@@ -199,6 +199,7 @@ def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> {
199199
// A 21-bit signed immediate where the least significant bit is zero.
200200
def simm21_lsb0_jal : Operand<OtherVT> {
201201
let ParserMatchClass = Simm21Lsb0JALAsmOperand;
202+
let PrintMethod = "printBranchOperand";
202203
let EncoderMethod = "getImmOpValueAsr1";
203204
let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
204205
let MCOperandPredicate = [{
@@ -207,8 +208,7 @@ def simm21_lsb0_jal : Operand<OtherVT> {
207208
return isShiftedInt<20, 1>(Imm);
208209
return MCOp.isBareSymbolRef();
209210
}];
210-
let OperandType = "OPERAND_SIMM21_LSB0";
211-
let OperandNamespace = "RISCVOp";
211+
let OperandType = "OPERAND_PCREL";
212212
}
213213

214214
def BareSymbol : AsmOperandClass {

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,7 @@ def uimm8_lsb000 : Operand<XLenVT>,
140140
def simm9_lsb0 : Operand<OtherVT>,
141141
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
142142
let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
143+
let PrintMethod = "printBranchOperand";
143144
let EncoderMethod = "getImmOpValueAsr1";
144145
let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
145146
let MCOperandPredicate = [{
@@ -149,6 +150,7 @@ def simm9_lsb0 : Operand<OtherVT>,
149150
return MCOp.isBareSymbolRef();
150151

151152
}];
153+
let OperandType = "OPERAND_PCREL";
152154
}
153155

154156
// A 9-bit unsigned immediate where the least significant three bits are zero.
@@ -200,6 +202,7 @@ def simm10_lsb0000nonzero : Operand<XLenVT>,
200202
def simm12_lsb0 : Operand<XLenVT>,
201203
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
202204
let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
205+
let PrintMethod = "printBranchOperand";
203206
let EncoderMethod = "getImmOpValueAsr1";
204207
let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
205208
let MCOperandPredicate = [{
@@ -208,6 +211,7 @@ def simm12_lsb0 : Operand<XLenVT>,
208211
return isShiftedInt<11, 1>(Imm);
209212
return MCOp.isBareSymbolRef();
210213
}];
214+
let OperandType = "OPERAND_PCREL";
211215
}
212216

213217
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,9 +132,7 @@ enum OperandType : unsigned {
132132
OPERAND_UIMM5,
133133
OPERAND_UIMM12,
134134
OPERAND_SIMM12,
135-
OPERAND_SIMM13_LSB0,
136135
OPERAND_UIMM20,
137-
OPERAND_SIMM21_LSB0,
138136
OPERAND_UIMMLOG2XLEN,
139137
OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN
140138
};

‎llvm/test/CodeGen/RISCV/compress.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -50,34 +50,34 @@ define i32 @simple_arith(i32 %a, i32 %b) #0 {
5050
define i32 @select(i32 %a, i32 *%b) #0 {
5151
; RV32IC-LABEL: <select>:
5252
; RV32IC: c.lw a2, 0(a1)
53-
; RV32IC-NEXT: c.beqz a2, 4
53+
; RV32IC-NEXT: c.beqz a2, 0x18
5454
; RV32IC-NEXT: c.mv a0, a2
5555
; RV32IC-NEXT: c.lw a2, 0(a1)
56-
; RV32IC-NEXT: c.bnez a2, 4
56+
; RV32IC-NEXT: c.bnez a2, 0x1e
5757
; RV32IC-NEXT: c.mv a0, a2
5858
; RV32IC-NEXT: c.lw a2, 0(a1)
59-
; RV32IC-NEXT: bltu a2, a0, 6
59+
; RV32IC-NEXT: bltu a2, a0, 0x26
6060
; RV32IC-NEXT: c.mv a0, a2
6161
; RV32IC-NEXT: c.lw a2, 0(a1)
62-
; RV32IC-NEXT: bgeu a0, a2, 6
62+
; RV32IC-NEXT: bgeu a0, a2, 0x2e
6363
; RV32IC-NEXT: c.mv a0, a2
6464
; RV32IC-NEXT: c.lw a2, 0(a1)
65-
; RV32IC-NEXT: bltu a0, a2, 6
65+
; RV32IC-NEXT: bltu a0, a2, 0x36
6666
; RV32IC-NEXT: c.mv a0, a2
6767
; RV32IC-NEXT: c.lw a2, 0(a1)
68-
; RV32IC-NEXT: bgeu a2, a0, 6
68+
; RV32IC-NEXT: bgeu a2, a0, 0x3e
6969
; RV32IC-NEXT: c.mv a0, a2
7070
; RV32IC-NEXT: c.lw a2, 0(a1)
71-
; RV32IC-NEXT: blt a2, a0, 6
71+
; RV32IC-NEXT: blt a2, a0, 0x46
7272
; RV32IC-NEXT: c.mv a0, a2
7373
; RV32IC-NEXT: c.lw a2, 0(a1)
74-
; RV32IC-NEXT: bge a0, a2, 6
74+
; RV32IC-NEXT: bge a0, a2, 0x4e
7575
; RV32IC-NEXT: c.mv a0, a2
7676
; RV32IC-NEXT: c.lw a2, 0(a1)
77-
; RV32IC-NEXT: blt a0, a2, 6
77+
; RV32IC-NEXT: blt a0, a2, 0x56
7878
; RV32IC-NEXT: c.mv a0, a2
7979
; RV32IC-NEXT: c.lw a1, 0(a1)
80-
; RV32IC-NEXT: bge a1, a0, 6
80+
; RV32IC-NEXT: bge a1, a0, 0x5e
8181
; RV32IC-NEXT: c.mv a0, a1
8282
; RV32IC-NEXT: c.jr ra
8383
%val1 = load volatile i32, i32* %b

‎llvm/test/MC/Disassembler/RISCV/branch-targets.txt

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -15,13 +15,13 @@ label1:
1515
bnez a0, label1
1616
bnez a0, label2
1717
# CHECK-LABEL: <label1>:
18-
# CHECK-NEXT: jal zero, 0 <label1>
19-
# CHECK-NEXT: jal zero, 20 <label2>
20-
# CHECK-NEXT: bne a0, zero, -8 <label1>
21-
# CHECK-NEXT: bne a0, zero, 12 <label2>
22-
# CHECK-NEXT: c.j -16 <label1>
23-
# CHECK-NEXT: c.j 6 <label2>
24-
# CHECK-NEXT: c.bnez a0, -20 <label1>
25-
# CHECK-NEXT: c.bnez a0, 2 <label2>
18+
# CHECK-NEXT: jal zero, 0x0 <label1>
19+
# CHECK-NEXT: jal zero, 0x18 <label2>
20+
# CHECK-NEXT: bne a0, zero, 0x0 <label1>
21+
# CHECK-NEXT: bne a0, zero, 0x18 <label2>
22+
# CHECK-NEXT: c.j 0x0 <label1>
23+
# CHECK-NEXT: c.j 0x18 <label2>
24+
# CHECK-NEXT: c.bnez a0, 0x0 <label1>
25+
# CHECK-NEXT: c.bnez a0, 0x18 <label2>
2626

2727
label2:

‎llvm/test/MC/RISCV/compress-cjal.s

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,14 +4,16 @@
44
# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
55
# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
66
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \
7-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
7+
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIASOBJ %s
88
# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
99
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases - \
10-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
10+
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INSTOBJ %s
1111

1212
# c.jal is an rv32 only instruction.
1313
jal ra, 2046
1414
# CHECK-BYTES: fd 2f
15+
# CHECK-ALIASOBJ: jal 0x7fe
1516
# CHECK-ALIAS: jal 2046
1617
# CHECK-INST: c.jal 2046
18+
# CHECK-INSTOBJ: c.jal 0x7fe
1719
# CHECK: # encoding: [0xfd,0x2f]

‎llvm/test/MC/RISCV/compress-rv32i.s

Lines changed: 26 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,24 @@
11
# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \
2-
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
2+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS,CHECK-ALIASASM %s
33
# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \
4-
# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
4+
# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-INSTASM %s
55
# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
66
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \
7-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
7+
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIASOBJ32 %s
88
# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
99
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases - \
10-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
10+
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INSTOBJ32 %s
1111

1212
# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \
13-
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
13+
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS,CHECK-ALIASASM %s
1414
# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \
15-
# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
15+
# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST,CHECK-INSTASM %s
1616
# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
1717
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d - \
18-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
18+
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIASOBJ64 %s
1919
# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
2020
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d -M no-aliases - \
21-
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
21+
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INSTOBJ64 %s
2222

2323
# CHECK-BYTES: 2e 85
2424
# CHECK-ALIAS: add a0, zero, a1
@@ -135,20 +135,32 @@ and s0, s0, a5
135135
and s0, a5, s0
136136

137137
# CHECK-BYTES: 01 b0
138-
# CHECK-ALIAS: j -2048
139-
# CHECK-INST: c.j -2048
138+
# CHECK-ALIASASM: j -2048
139+
# CHECK-ALIASOBJ32: j 0xfffff826
140+
# CHECK-ALIASOBJ64: j 0xfffffffffffff826
141+
# CHECK-INSTASM: c.j -2048
142+
# CHECK-INSTOBJ32: c.j 0xfffff826
143+
# CHECK-INSTOBJ64: c.j 0xfffffffffffff826
140144
# CHECK: # encoding: [0x01,0xb0]
141145
jal zero, -2048
142146

143147
# CHECK-BYTES: 01 d0
144-
# CHECK-ALIAS: beqz s0, -256
145-
# CHECK-INST: c.beqz s0, -256
148+
# CHECK-ALIASASM: beqz s0, -256
149+
# CHECK-ALIASOBJ32: beqz s0, 0xffffff28
150+
# CHECK-ALIASOBJ64: beqz s0, 0xffffffffffffff28
151+
# CHECK-INSTASM: c.beqz s0, -256
152+
# CHECK-INSTOBJ32: c.beqz s0, 0xffffff28
153+
# CHECK-INSTOBJ64: c.beqz s0, 0xffffffffffffff28
146154
# CHECK: # encoding: [0x01,0xd0]
147155
beq s0, zero, -256
148156

149157
# CHECK-BYTES: 7d ec
150-
# CHECk-ALIAS: bnez s0, 254
151-
# CHECK-INST: c.bnez s0, 254
158+
# CHECK-ALIASASM: bnez s0, 254
159+
# CHECK-ALIASOBJ32: bnez s0, 0x128
160+
# CHECK-ALIASOBJ64: bnez s0, 0x128
161+
# CHECK-INSTASM: c.bnez s0, 254
162+
# CHECK-INSTOBJ32: c.bnez s0, 0x128
163+
# CHECK-INSTOBJ64: c.bnez s0, 0x128
152164
# CHECK: # encoding: [0x7d,0xec]
153165
bne s0, zero, 254
154166

‎llvm/test/MC/RISCV/fixups-compressed.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,13 @@
1010
# CHECK-INSTR: c.j 0
1111
c.j .LBB0_2
1212
# CHECK: fixup A - offset: 0, value: func1, kind: fixup_riscv_rvc_jump
13-
# CHECK-INSTR: c.jal 6
13+
# CHECK-INSTR: c.jal 0x8
1414
c.jal func1
1515
# CHECK-FIXUP: fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch
16-
# CHECK-INSTR: c.beqz a3, -4
16+
# CHECK-INSTR: c.beqz a3, 0x0
1717
c.beqz a3, .LBB0_2
1818
# CHECK-FIXUP: fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch
19-
# CHECK-INSTR: c.bnez a5, -6
19+
# CHECK-INSTR: c.bnez a5, 0x0
2020
c.bnez a5, .LBB0_2
2121

2222
func1:

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