Skip to content

Commit be1082c

Browse files
SisyphSisyph
committed
[AMDGPU] gfx11 VOPC instructions
Supports encoding existing instrutions on gfx11 and MC support for the new VOPC dpp instructions. Patch 19/N for upstreaming of AMDGPU gfx11 architecture Depends on D126978 Reviewed By: rampitec, #amdgpu Differential Revision: https://reviews.llvm.org/D126989
1 parent 25c8a06 commit be1082c

File tree

11 files changed

+62165
-47
lines changed

11 files changed

+62165
-47
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 34 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1762,9 +1762,24 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17621762
AMDGPUOperand::Ptr defaultBoundCtrl() const;
17631763
AMDGPUOperand::Ptr defaultFI() const;
17641764
void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1765-
void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); }
1766-
void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1767-
void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) { cvtVOP3DPP(Inst, Operands, true); }
1765+
void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {
1766+
cvtDPP(Inst, Operands, true);
1767+
}
1768+
void cvtVOPCNoDstDPP(MCInst &Inst, const OperandVector &Operands,
1769+
bool IsDPP8 = false);
1770+
void cvtVOPCNoDstDPP8(MCInst &Inst, const OperandVector &Operands) {
1771+
cvtVOPCNoDstDPP(Inst, Operands, true);
1772+
}
1773+
void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
1774+
bool IsDPP8 = false);
1775+
void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {
1776+
cvtVOP3DPP(Inst, Operands, true);
1777+
}
1778+
void cvtVOPC64NoDstDPP(MCInst &Inst, const OperandVector &Operands,
1779+
bool IsDPP8 = false);
1780+
void cvtVOPC64NoDstDPP8(MCInst &Inst, const OperandVector &Operands) {
1781+
cvtVOPC64NoDstDPP(Inst, Operands, true);
1782+
}
17681783

17691784
OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
17701785
AMDGPUOperand::ImmTy Type);
@@ -8594,6 +8609,14 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFI() const {
85948609
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppFi);
85958610
}
85968611

8612+
// Add dummy $old operand
8613+
void AMDGPUAsmParser::cvtVOPC64NoDstDPP(MCInst &Inst,
8614+
const OperandVector &Operands,
8615+
bool IsDPP8) {
8616+
Inst.addOperand(MCOperand::createReg(0));
8617+
cvtVOP3DPP(Inst, Operands, IsDPP8);
8618+
}
8619+
85978620
void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
85988621
OptionalImmIndexMap OptionalIdx;
85998622
unsigned Opc = Inst.getOpcode();
@@ -8660,6 +8683,14 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bo
86608683
}
86618684
}
86628685

8686+
// Add dummy $old operand
8687+
void AMDGPUAsmParser::cvtVOPCNoDstDPP(MCInst &Inst,
8688+
const OperandVector &Operands,
8689+
bool IsDPP8) {
8690+
Inst.addOperand(MCOperand::createReg(0));
8691+
cvtDPP(Inst, Operands, IsDPP8);
8692+
}
8693+
86638694
void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
86648695
OptionalImmIndexMap OptionalIdx;
86658696

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 29 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -444,6 +444,8 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
444444
if (Res) {
445445
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
446446
convertVOP3PDPPInst(MI);
447+
else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
448+
convertVOPCDPPInst(MI);
447449
break;
448450
}
449451
}
@@ -479,8 +481,11 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
479481
if (Res) break;
480482

481483
Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address);
482-
if (Res)
484+
if (Res) {
485+
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
486+
convertVOPCDPPInst(MI);
483487
break;
488+
}
484489

485490
Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
486491
if (Res) { IsSDWA = true; break; }
@@ -734,6 +739,8 @@ DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
734739
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
735740
if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) {
736741
convertVOP3PDPPInst(MI);
742+
} else if (MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) {
743+
convertVOPCDPPInst(MI);
737744
} else {
738745
// Insert dummy unused src modifiers.
739746
if (MI.getNumOperands() < DescNumOps &&
@@ -937,6 +944,27 @@ DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const {
937944
return MCDisassembler::Success;
938945
}
939946

947+
// Create dummy old operand and insert optional operands
948+
DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const {
949+
unsigned Opc = MI.getOpcode();
950+
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
951+
952+
if (MI.getNumOperands() < DescNumOps &&
953+
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1)
954+
insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
955+
956+
if (MI.getNumOperands() < DescNumOps &&
957+
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
958+
insertNamedMCOperand(MI, MCOperand::createImm(0),
959+
AMDGPU::OpName::src0_modifiers);
960+
961+
if (MI.getNumOperands() < DescNumOps &&
962+
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
963+
insertNamedMCOperand(MI, MCOperand::createImm(0),
964+
AMDGPU::OpName::src1_modifiers);
965+
return MCDisassembler::Success;
966+
}
967+
940968
DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI,
941969
int ImmLitIdx) const {
942970
assert(HasLiteral && "Should have decoded a literal");

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,7 @@ class AMDGPUDisassembler : public MCDisassembler {
163163
DecodeStatus convertDPP8Inst(MCInst &MI) const;
164164
DecodeStatus convertMIMGInst(MCInst &MI) const;
165165
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const;
166+
DecodeStatus convertVOPCDPPInst(MCInst &MI) const;
166167

167168
MCOperand decodeOperand_VGPR_32(unsigned Val) const;
168169
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 41 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -382,7 +382,7 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
382382
O << " ";
383383
}
384384

385-
printOperand(MI, OpNo, STI, O);
385+
printRegularOperand(MI, OpNo, STI, O);
386386

387387
// Print default vcc/vcc_lo operand.
388388
switch (Opcode) {
@@ -421,7 +421,7 @@ void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
421421
else
422422
O << "_e32 ";
423423

424-
printOperand(MI, OpNo, STI, O);
424+
printRegularOperand(MI, OpNo, STI, O);
425425
}
426426

427427
void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
@@ -625,17 +625,41 @@ void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
625625
}
626626
}
627627

628+
bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
629+
unsigned OpNo) const {
630+
return OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) &&
631+
(Desc.TSFlags & SIInstrFlags::VOPC) &&
632+
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
633+
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
634+
}
635+
628636
// Print default vcc/vcc_lo operand of VOPC.
629637
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
630638
const MCSubtargetInfo &STI,
631639
raw_ostream &O) {
632-
// Print default vcc/vcc_lo operand of VOPC.
633-
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
634-
if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
640+
unsigned Opc = MI->getOpcode();
641+
const MCInstrDesc &Desc = MII.get(Opc);
642+
int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
643+
// 0, 1 and 2 are the first printed operands in different cases
644+
// If there are printed modifiers, printOperandAndFPInputMods or
645+
// printOperandAndIntInputMods will be called instead
646+
if ((OpNo == 0 ||
647+
(OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP)) ||
648+
(OpNo == 2 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) &&
649+
(Desc.TSFlags & SIInstrFlags::VOPC) &&
635650
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
636651
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
637652
printDefaultVccOperand(true, STI, O);
638653

654+
printRegularOperand(MI, OpNo, STI, O);
655+
}
656+
657+
// Print operands after vcc or modifier handling.
658+
void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
659+
const MCSubtargetInfo &STI,
660+
raw_ostream &O) {
661+
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
662+
639663
if (OpNo >= MI->getNumOperands()) {
640664
O << "/*Missing OP" << OpNo << "*/";
641665
return;
@@ -788,6 +812,10 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
788812
unsigned OpNo,
789813
const MCSubtargetInfo &STI,
790814
raw_ostream &O) {
815+
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
816+
if (needsImpliedVcc(Desc, OpNo))
817+
printDefaultVccOperand(true, STI, O);
818+
791819
unsigned InputModifiers = MI->getOperand(OpNo).getImm();
792820

793821
// Use 'neg(...)' instead of '-' to avoid ambiguity.
@@ -810,7 +838,7 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
810838

811839
if (InputModifiers & SISrcMods::ABS)
812840
O << '|';
813-
printOperand(MI, OpNo + 1, STI, O);
841+
printRegularOperand(MI, OpNo + 1, STI, O);
814842
if (InputModifiers & SISrcMods::ABS)
815843
O << '|';
816844

@@ -823,10 +851,14 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
823851
unsigned OpNo,
824852
const MCSubtargetInfo &STI,
825853
raw_ostream &O) {
854+
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
855+
if (needsImpliedVcc(Desc, OpNo))
856+
printDefaultVccOperand(true, STI, O);
857+
826858
unsigned InputModifiers = MI->getOperand(OpNo).getImm();
827859
if (InputModifiers & SISrcMods::SEXT)
828860
O << "sext(";
829-
printOperand(MI, OpNo + 1, STI, O);
861+
printRegularOperand(MI, OpNo + 1, STI, O);
830862
if (InputModifiers & SISrcMods::SEXT)
831863
O << ')';
832864

@@ -1259,9 +1291,9 @@ void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
12591291
void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
12601292
const MCSubtargetInfo &STI,
12611293
raw_ostream &O) {
1262-
printOperand(MI, OpNo, STI, O);
1294+
printRegularOperand(MI, OpNo, STI, O);
12631295
O << ", ";
1264-
printOperand(MI, OpNo + 1, STI, O);
1296+
printRegularOperand(MI, OpNo + 1, STI, O);
12651297
}
12661298

12671299
void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "llvm/MC/MCInstPrinter.h"
1616

1717
namespace llvm {
18+
class MCInstrDesc;
1819

1920
class AMDGPUInstPrinter : public MCInstPrinter {
2021
public:
@@ -117,6 +118,8 @@ class AMDGPUInstPrinter : public MCInstPrinter {
117118
raw_ostream &O);
118119
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
119120
raw_ostream &O);
121+
void printRegularOperand(const MCInst *MI, unsigned OpNo,
122+
const MCSubtargetInfo &STI, raw_ostream &O);
120123
void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum,
121124
const MCSubtargetInfo &STI, raw_ostream &O) {
122125
printOperand(MI, OpNum, STI, O);
@@ -173,6 +176,7 @@ class AMDGPUInstPrinter : public MCInstPrinter {
173176
raw_ostream &O);
174177
void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
175178
raw_ostream &O);
179+
bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
176180
void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
177181
raw_ostream &O);
178182
void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,

0 commit comments

Comments
 (0)