---

yaml
---
r: 224490
b: refs/heads/beta
c: fcf4a7e
h: refs/heads/master
v: v3

Author: Gankra

[refs]

@@ -23,7 +23,7 @@ refs/tags/0.9: 36870b185fc5f5486636d4515f0e22677493f225
 refs/tags/0.10: ac33f2b15782272ae348dbd7b14b8257b2148b5a
 refs/tags/0.11.0: e1247cb1d0d681be034adb4b558b5a0c0d5720f9
 refs/tags/0.12.0: f0c419429ef30723ceaf6b42f9b5a2aeb5d2e2d1
-refs/heads/beta: 498e44d87a93183ac04690e09a39fee47dfe85b0
+refs/heads/beta: fcf4a7e5c87cf80ff8d7c142fbdfd8fd398ad3a7
 refs/tags/1.0.0-alpha: e42bd6d93a1d3433c486200587f8f9e12590a4d7
 refs/heads/tmp: 938f5d7af401e2d8238522fed4a612943b6e77fd
 refs/tags/1.0.0-alpha.2: 4c705f6bc559886632d3871b04f58aab093bfa2f

branches/beta/atomics.md

@@ -89,8 +89,6 @@ However there's a third potential state that the hardware enables:
 
 * `y = 2`: (thread 2 saw `x = 2`, but not `y = 3`, and then overwrote `y = 3`)
 
-```
-
 It's worth noting that different kinds of CPU provide different guarantees. It
 is common to seperate hardware into two categories: strongly-ordered and weakly-
 ordered. Most notably x86/64 provides strong ordering guarantees, while ARM and