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DirrekeDirreke
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add a csky-unknown-linux-gnuabiv2 target
1 parent 3071e0a commit d16409f

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30 files changed

+313
-4
lines changed

30 files changed

+313
-4
lines changed

‎compiler/rustc_codegen_gcc/example/alloc_system.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
target_arch = "mips",
1313
target_arch = "mips32r6",
1414
target_arch = "powerpc",
15+
target_arch = "csky"
1516
target_arch = "powerpc64"))]
1617
const MIN_ALIGN: usize = 8;
1718
#[cfg(any(target_arch = "x86_64",

‎compiler/rustc_codegen_gcc/src/asm.rs

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -597,6 +597,8 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
597597
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
598598
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
599599
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
600+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => "r",
601+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => "f",
600602
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "d", // more specific than "r"
601603
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
602604
InlineAsmRegClass::Msp430(Msp430InlineAsmRegClass::reg) => "r",
@@ -673,6 +675,8 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
673675
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => cx.type_i32(),
674676
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => cx.type_i32(),
675677
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => cx.type_i32(),
678+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => cx.type_i32(),
679+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => cx.type_f32(),
676680
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
677681
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
678682
InlineAsmRegClass::Msp430(_) => unimplemented!(),
@@ -860,6 +864,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
860864
InlineAsmRegClass::S390x(_) => None,
861865
InlineAsmRegClass::Msp430(_) => None,
862866
InlineAsmRegClass::M68k(_) => None,
867+
InlineAsmRegClass::CSKY(_) => None,
863868
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
864869
bug!("LLVM backend does not support SPIR-V")
865870
}

‎compiler/rustc_codegen_llvm/src/asm.rs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
261261
InlineAsmArch::M68k => {
262262
constraints.push("~{ccr}".to_string());
263263
}
264+
InlineAsmArch::CSKY => {} // https://github.com/llvm/llvm-project/blob/8b76aea8d8b1b71f6220bc2845abc749f18a19b7/clang/lib/Basic/Targets/CSKY.h getClobers()
264265
}
265266
}
266267
if !options.contains(InlineAsmOptions::NOMEM) {
@@ -693,6 +694,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
693694
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
694695
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
695696
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
697+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => "r",
698+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => "f",
696699
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
697700
bug!("LLVM backend does not support SPIR-V")
698701
}
@@ -792,6 +795,7 @@ fn modifier_to_llvm(
792795
bug!("LLVM backend does not support SPIR-V")
793796
}
794797
InlineAsmRegClass::M68k(_) => None,
798+
InlineAsmRegClass::CSKY(_) => None,
795799
InlineAsmRegClass::Err => unreachable!(),
796800
}
797801
}
@@ -868,6 +872,8 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
868872
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => cx.type_i32(),
869873
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => cx.type_i32(),
870874
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => cx.type_i32(),
875+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => cx.type_i32(),
876+
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => cx.type_f32(),
871877
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
872878
bug!("LLVM backend does not support SPIR-V")
873879
}

‎compiler/rustc_llvm/build.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ const OPTIONAL_COMPONENTS: &[&str] = &[
1212
"avr",
1313
"loongarch",
1414
"m68k",
15+
"csky",
1516
"mips",
1617
"powerpc",
1718
"systemz",

‎compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,12 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
105105
#define SUBTARGET_M68K
106106
#endif
107107

108+
#ifdef LLVM_COMPONENT_CSKY
109+
#define SUBTARGET_CSKY SUBTARGET(CSKY)
110+
#else
111+
#define SUBTARGET_CSKY
112+
#endif
113+
108114
#ifdef LLVM_COMPONENT_MIPS
109115
#define SUBTARGET_MIPS SUBTARGET(Mips)
110116
#else
@@ -159,6 +165,7 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
159165
SUBTARGET_AARCH64 \
160166
SUBTARGET_AVR \
161167
SUBTARGET_M68K \
168+
SUBTARGET_CSKY \
162169
SUBTARGET_MIPS \
163170
SUBTARGET_PPC \
164171
SUBTARGET_SYSTEMZ \

‎compiler/rustc_llvm/src/lib.rs

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,14 @@ pub fn initialize_available_targets() {
102102
LLVMInitializeM68kAsmPrinter,
103103
LLVMInitializeM68kAsmParser
104104
);
105+
init_target!(
106+
llvm_component = "csky",
107+
LLVMInitializeCSKYTargetInfo,
108+
LLVMInitializeCSKYTarget,
109+
LLVMInitializeCSKYTargetMC,
110+
LLVMInitializeCSKYAsmPrinter,
111+
LLVMInitializeCSKYAsmParser
112+
);
105113
init_target!(
106114
llvm_component = "loongarch",
107115
LLVMInitializeLoongArchTargetInfo,

‎compiler/rustc_target/src/abi/call/csky.rs

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
//see https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/CSKY/CSKYCallingConv.td
2+
use crate::abi::call::{ArgAbi, FnAbi};
3+
4+
fn classify_ret<Ty>(ret: &mut ArgAbi<'_, Ty>) {
5+
if ret.layout.is_aggregate() || ret.layout.size.bits() > 64 {
6+
ret.make_indirect();
7+
} else {
8+
ret.extend_integer_width_to(32);
9+
}
10+
}
11+
12+
fn classify_arg<Ty>(arg: &mut ArgAbi<'_, Ty>) {
13+
if arg.layout.is_aggregate() || arg.layout.size.bits() > 64 {
14+
arg.make_indirect();
15+
} else {
16+
arg.extend_integer_width_to(32);
17+
}
18+
}
19+
20+
pub fn compute_abi_info<Ty>(fn_abi: &mut FnAbi<'_, Ty>) {
21+
if !fn_abi.ret.is_ignore() {
22+
classify_ret(&mut fn_abi.ret);
23+
}
24+
25+
for arg in fn_abi.args.iter_mut() {
26+
if arg.is_ignore() {
27+
continue;
28+
}
29+
classify_arg(arg);
30+
}
31+
}

‎compiler/rustc_target/src/abi/call/mod.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ mod amdgpu;
99
mod arm;
1010
mod avr;
1111
mod bpf;
12+
mod csky;
1213
mod hexagon;
1314
mod loongarch;
1415
mod m68k;
@@ -712,6 +713,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
712713
"avr" => avr::compute_abi_info(self),
713714
"loongarch64" => loongarch::compute_abi_info(cx, self),
714715
"m68k" => m68k::compute_abi_info(self),
716+
"csky" => csky::compute_abi_info(self),
715717
"mips" | "mips32r6" => mips::compute_abi_info(cx, self),
716718
"mips64" | "mips64r6" => mips64::compute_abi_info(cx, self),
717719
"powerpc" => powerpc::compute_abi_info(self),

‎compiler/rustc_target/src/asm/csky.rs

Lines changed: 142 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,142 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
use rustc_macros::HashStable_Generic;
3+
use rustc_span::Symbol;
4+
use std::fmt;
5+
6+
def_reg_class! {
7+
CSKY CSKYInlineAsmRegClass {
8+
reg,
9+
freg,
10+
}
11+
}
12+
13+
impl CSKYInlineAsmRegClass {
14+
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
15+
&[]
16+
}
17+
18+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
19+
None
20+
}
21+
22+
pub fn suggest_modifier(
23+
self,
24+
_arch: InlineAsmArch,
25+
_ty: InlineAsmType,
26+
) -> Option<(char, &'static str)> {
27+
None
28+
}
29+
30+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
31+
None
32+
}
33+
34+
pub fn supported_types(
35+
self,
36+
_arch: InlineAsmArch,
37+
) -> &'static [(InlineAsmType, Option<Symbol>)] {
38+
match self {
39+
Self::reg => types! { _: I8, I16, I32, I64, F32, F64; },
40+
Self::freg => types! { _: F32, F64; },
41+
}
42+
}
43+
}
44+
45+
// The reserved registers are taken from <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp#79>
46+
def_regs! {
47+
CSKY CSKYInlineAsmReg CSKYInlineAsmRegClass {
48+
r0: reg = ["r0","a0"],
49+
r1: reg = ["r1","a1"],
50+
r2: reg = ["r2","a2"],
51+
r3: reg = ["r3","a3"],
52+
r4: reg = ["r4","l0"],
53+
r5: reg = ["r5","l1"],
54+
r6: reg = ["r6","l2"],
55+
// r7: reg = ["r7","l3"],
56+
// r8: reg = ["r8","l4"],
57+
// r9: reg = ["r9","l5"],
58+
// r10: reg = ["r10","l6"],
59+
// r11: reg = ["r11","l7"],
60+
// r12: reg = ["r12","t0"],
61+
// r13: reg = ["r13","t1"],
62+
// r14: reg = ["r14","sp"],
63+
// r15: reg = ["r15","lr"],
64+
// r16: reg = ["r16","l8"],
65+
// r17: reg = ["r17","l9"],
66+
// r18: reg = ["r18","t2"],
67+
// r19: reg = ["r19","t3"],
68+
// r20: reg = ["r20","t4"],
69+
// r21: reg = ["r21","t5"],
70+
// r22: reg = ["r22","t6"],
71+
// r23: reg = ["r23","t7", "fp"],
72+
// r24: reg = ["r24","t8", "sop"],
73+
// r25: reg = ["r25","tp", "bsp"],
74+
// r26: reg = ["r26"],
75+
// r27: reg = ["r27"],
76+
// r28: reg = ["r28","gb", "rgb", "rdb"],
77+
// r29: reg = ["r29","tb", "rtb"],
78+
// r30: reg = ["r30","svbr"],
79+
// r31: reg = ["r31","tls"],
80+
f0: freg = ["fr0","vr0"],
81+
f1: freg = ["fr1","vr1"],
82+
f2: freg = ["fr2","vr2"],
83+
f3: freg = ["fr3","vr3"],
84+
f4: freg = ["fr4","vr4"],
85+
f5: freg = ["fr5","vr5"],
86+
f6: freg = ["fr6","vr6"],
87+
f7: freg = ["fr7","vr7"],
88+
f8: freg = ["fr8","vr8"],
89+
f9: freg = ["fr9","vr9"],
90+
f10: freg = ["fr10","vr10"],
91+
f11: freg = ["fr11","vr11"],
92+
f12: freg = ["fr12","vr12"],
93+
f13: freg = ["fr13","vr13"],
94+
f14: freg = ["fr14","vr14"],
95+
f15: freg = ["fr15","vr15"],
96+
f16: freg = ["fr16","vr16"],
97+
f17: freg = ["fr17","vr17"],
98+
f18: freg = ["fr18","vr18"],
99+
f19: freg = ["fr19","vr19"],
100+
f20: freg = ["fr20","vr20"],
101+
f21: freg = ["fr21","vr21"],
102+
f22: freg = ["fr22","vr22"],
103+
f23: freg = ["fr23","vr23"],
104+
f24: freg = ["fr24","vr24"],
105+
f25: freg = ["fr25","vr25"],
106+
f26: freg = ["fr26","vr26"],
107+
f27: freg = ["fr27","vr27"],
108+
f28: freg = ["fr28","vr28"],
109+
f29: freg = ["fr29","vr29"],
110+
f30: freg = ["fr30","vr30"],
111+
f31: freg = ["fr31","vr31"],
112+
#error = ["r7", "l3"] =>
113+
"the base pointer cannot be used as an operand for inline asm",
114+
#error = ["r8","l4"] =>
115+
"the frame pointer cannot be used as an operand for inline asm",
116+
#error = ["r14","sp"] =>
117+
"the stack pointer cannot be used as an operand for inline asm",
118+
#error = ["r15","lr"] =>
119+
"the link register cannot be used as an operand for inline asm",
120+
#error = ["r31","tls"] =>
121+
"reserver for tls",
122+
#error = ["r28", "gb", "rgb", "rdb"] =>
123+
"the global pointer cannot be used as an operand for inline asm",
124+
#error = ["r9","l5", "r10","l6", "r11","l7", "r12","t0", "r13","t1"] =>
125+
"reserved (no E2)",
126+
#error = ["r16","l8", "r17","l9", "r18","t2", "r19","t3", "r20","t4", "r21","t5", "r22","t6", "r23","t7", "fp", "r24","t8", "sop", "r25","tp", "bsp"] =>
127+
"reserved (no HighRegisters)",
128+
#error = ["r26","r27","r29","tb", "rtb", "r30","svbr"] =>
129+
"reserved by the ABI",
130+
}
131+
}
132+
133+
impl CSKYInlineAsmReg {
134+
pub fn emit(
135+
self,
136+
out: &mut dyn fmt::Write,
137+
_arch: InlineAsmArch,
138+
_modifier: Option<char>,
139+
) -> fmt::Result {
140+
out.write_str(self.name())
141+
}
142+
}

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