Skip to content

Commit e16ccba

Browse files
committed
Support -Ctarget-cpu
1 parent cdc0aa1 commit e16ccba

File tree

1 file changed

+8
-3
lines changed

1 file changed

+8
-3
lines changed

src/lib.rs

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -273,9 +273,14 @@ fn build_isa(sess: &Session, backend_config: &BackendConfig) -> Box<dyn isa::Tar
273273

274274
let variant = cranelift_codegen::isa::BackendVariant::MachInst;
275275
let mut isa_builder = cranelift_codegen::isa::lookup_variant(target_triple, variant).unwrap();
276-
// Don't use "haswell", as it implies `has_lzcnt`.macOS CI is still at Ivy Bridge EP, so `lzcnt`
277-
// is interpreted as `bsr`.
278-
isa_builder.enable("nehalem").unwrap();
276+
277+
if let Some(target_cpu) = sess.opts.cg.target_cpu.as_ref() {
278+
isa_builder.enable(target_cpu).unwrap();
279+
} else {
280+
// Don't use "haswell" as the default, as it implies `has_lzcnt`.
281+
// macOS CI is still at Ivy Bridge EP, so `lzcnt` is interpreted as `bsr`.
282+
isa_builder.enable("nehalem").unwrap();
283+
}
279284
isa_builder.finish(flags)
280285
}
281286

0 commit comments

Comments
 (0)