---

yaml
---
r: 236073
b: refs/heads/stable
c: fcf4a7e
h: refs/heads/master
i:
  236071: c18d64e
v: v3

Author: Gankra

[refs]

@@ -29,7 +29,7 @@ refs/heads/tmp: afae2ff723393b3ab4ccffef6ac7c6d1809e2da0
 refs/tags/1.0.0-alpha.2: 4c705f6bc559886632d3871b04f58aab093bfa2f
 refs/tags/homu-tmp: f859507de8c410b648d934d8f5ec1c52daac971d
 refs/tags/1.0.0-beta: 8cbb92b53468ee2b0c2d3eeb8567005953d40828
-refs/heads/stable: 498e44d87a93183ac04690e09a39fee47dfe85b0
+refs/heads/stable: fcf4a7e5c87cf80ff8d7c142fbdfd8fd398ad3a7
 refs/tags/1.0.0: 55bd4f8ff2b323f317ae89e254ce87162d52a375
 refs/tags/1.1.0: bc3c16f09287e5545c1d3f76b7abd54f2eca868b
 refs/tags/1.2.0: f557861f822c34f07270347b94b5280de20a597e

branches/stable/atomics.md

@@ -89,8 +89,6 @@ However there's a third potential state that the hardware enables:
 
 * `y = 2`: (thread 2 saw `x = 2`, but not `y = 3`, and then overwrote `y = 3`)
 
-```
-
 It's worth noting that different kinds of CPU provide different guarantees. It
 is common to seperate hardware into two categories: strongly-ordered and weakly-
 ordered. Most notably x86/64 provides strong ordering guarantees, while ARM and