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[AArch64][GlobalISel] Support the 'returned' parameter attribute.
On AArch64 (which seems to be the only target that supports it), this attribute allows codegen to avoid saving/restoring the value in x0 across a call. Gives a 0.1% geomean -Os code size improvement on CTMark. Differential Revision: https://reviews.llvm.org/D96099
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+186
-23
lines changed

7 files changed

+186
-23
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -266,13 +266,13 @@ class CallLowering {
266266
///
267267
/// \return True if everything has succeeded, false otherwise.
268268
bool handleAssignments(MachineIRBuilder &MIRBuilder,
269-
SmallVectorImpl<ArgInfo> &Args,
270-
ValueHandler &Handler) const;
269+
SmallVectorImpl<ArgInfo> &Args, ValueHandler &Handler,
270+
Register ThisReturnReg = Register()) const;
271271
bool handleAssignments(CCState &CCState,
272272
SmallVectorImpl<CCValAssign> &ArgLocs,
273273
MachineIRBuilder &MIRBuilder,
274-
SmallVectorImpl<ArgInfo> &Args,
275-
ValueHandler &Handler) const;
274+
SmallVectorImpl<ArgInfo> &Args, ValueHandler &Handler,
275+
Register ThisReturnReg = Register()) const;
276276

277277
/// Analyze passed or returned values from a call, supplied in \p ArgInfo,
278278
/// incorporating info about the passed values into \p CCState.
@@ -456,6 +456,10 @@ class CallLowering {
456456
ArrayRef<Register> ResRegs,
457457
ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
458458
std::function<unsigned()> GetCalleeReg) const;
459+
460+
/// For targets which support the "returned" parameter attribute, returns
461+
/// true if the given type is a valid one to use with "returned".
462+
virtual bool isTypeIsValidForThisReturn(EVT Ty) const { return false; }
459463
};
460464

461465
} // end namespace llvm

‎llvm/include/llvm/CodeGen/TargetCallingConv.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ namespace ISD {
119119
void setNest() { IsNest = 1; }
120120

121121
bool isReturned() const { return IsReturned; }
122-
void setReturned() { IsReturned = 1; }
122+
void setReturned(bool V = true) { IsReturned = V; }
123123

124124
bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; }
125125
void setInConsecutiveRegs(bool Flag = true) { IsInConsecutiveRegs = Flag; }

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 27 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -170,6 +170,11 @@ void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
170170
Flags.setByValAlign(FrameAlign);
171171
}
172172
Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
173+
174+
// Don't try to use the returned attribute if the argument is marked as
175+
// swiftself, since it won't be passed in x0.
176+
if (Flags.isSwiftSelf())
177+
Flags.setReturned(false);
173178
}
174179

175180
template void
@@ -225,19 +230,22 @@ void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
225230

226231
bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
227232
SmallVectorImpl<ArgInfo> &Args,
228-
ValueHandler &Handler) const {
233+
ValueHandler &Handler,
234+
Register ThisReturnReg) const {
229235
MachineFunction &MF = MIRBuilder.getMF();
230236
const Function &F = MF.getFunction();
231237
SmallVector<CCValAssign, 16> ArgLocs;
232238
CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
233-
return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler);
239+
return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler,
240+
ThisReturnReg);
234241
}
235242

236243
bool CallLowering::handleAssignments(CCState &CCInfo,
237244
SmallVectorImpl<CCValAssign> &ArgLocs,
238245
MachineIRBuilder &MIRBuilder,
239246
SmallVectorImpl<ArgInfo> &Args,
240-
ValueHandler &Handler) const {
247+
ValueHandler &Handler,
248+
Register ThisReturnReg) const {
241249
MachineFunction &MF = MIRBuilder.getMF();
242250
const Function &F = MF.getFunction();
243251
const DataLayout &DL = F.getParent()->getDataLayout();
@@ -330,6 +338,15 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
330338
if (PartIdx == NumParts - 1)
331339
Flags.setSplitEnd();
332340
}
341+
342+
// TODO: Also check if there is a valid extension that preserves the
343+
// bits. However currently this call lowering doesn't support non-exact
344+
// split parts, so that can't be tested.
345+
if (OrigFlags.isReturned() &&
346+
(NumParts * NewVT.getSizeInBits() != CurVT.getSizeInBits())) {
347+
Flags.setReturned(false);
348+
}
349+
333350
Args[i].Regs.push_back(Unmerge.getReg(PartIdx));
334351
Args[i].Flags.push_back(Flags);
335352
if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full,
@@ -394,6 +411,13 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
394411

395412
assert(VA.isRegLoc() && "custom loc should have been handled already");
396413

414+
if (i == 0 && ThisReturnReg.isValid() &&
415+
Handler.isIncomingArgumentHandler() &&
416+
isTypeIsValidForThisReturn(VAVT)) {
417+
Handler.assignValueToReg(Args[i].Regs[i], ThisReturnReg, VA);
418+
continue;
419+
}
420+
397421
// GlobalISel does not currently work for scalable vectors.
398422
if (OrigVT.getFixedSizeInBits() >= VAVT.getFixedSizeInBits() ||
399423
!Handler.isIncomingArgumentHandler()) {

‎llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Lines changed: 52 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -152,6 +152,16 @@ struct CallReturnHandler : public IncomingArgHandler {
152152
MachineInstrBuilder MIB;
153153
};
154154

155+
/// A special return arg handler for "returned" attribute arg calls.
156+
struct ReturnedArgCallReturnHandler : public CallReturnHandler {
157+
ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
158+
MachineRegisterInfo &MRI,
159+
MachineInstrBuilder MIB, CCAssignFn *AssignFn)
160+
: CallReturnHandler(MIRBuilder, MRI, MIB, AssignFn) {}
161+
162+
void markPhysRegUsed(MCRegister PhysReg) override {}
163+
};
164+
155165
struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
156166
OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
157167
MachineInstrBuilder MIB, CCAssignFn *AssignFn,
@@ -785,6 +795,24 @@ static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
785795
return AArch64::TCRETURNri;
786796
}
787797

798+
static const uint32_t *
799+
getMaskForArgs(SmallVectorImpl<AArch64CallLowering::ArgInfo> &OutArgs,
800+
AArch64CallLowering::CallLoweringInfo &Info,
801+
const AArch64RegisterInfo &TRI, MachineFunction &MF) {
802+
const uint32_t *Mask;
803+
if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) {
804+
// For 'this' returns, use the X0-preserving mask if applicable
805+
Mask = TRI.getThisReturnPreservedMask(MF, Info.CallConv);
806+
if (!Mask) {
807+
OutArgs[0].Flags[0].setReturned(false);
808+
Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
809+
}
810+
} else {
811+
Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
812+
}
813+
return Mask;
814+
}
815+
788816
bool AArch64CallLowering::lowerTailCall(
789817
MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
790818
SmallVectorImpl<ArgInfo> &OutArgs) const {
@@ -878,6 +906,8 @@ bool AArch64CallLowering::lowerTailCall(
878906
if (!handleAssignments(MIRBuilder, OutArgs, Handler))
879907
return false;
880908

909+
Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
910+
881911
if (Info.IsVarArg && Info.IsMustTailCall) {
882912
// Now we know what's being passed to the function. Add uses to the call for
883913
// the forwarded registers that we *aren't* passing as parameters. This will
@@ -979,21 +1009,24 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
9791009
MIB.add(Info.Callee);
9801010

9811011
// Tell the call which registers are clobbered.
982-
auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
983-
const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv);
984-
if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
985-
TRI->UpdateCustomCallPreservedMask(MF, &Mask);
986-
MIB.addRegMask(Mask);
987-
988-
if (TRI->isAnyArgRegReserved(MF))
989-
TRI->emitReservedArgRegCallError(MF);
1012+
const uint32_t *Mask;
1013+
const auto *TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
9901014

9911015
// Do the actual argument marshalling.
9921016
OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
9931017
AssignFnVarArg, false);
9941018
if (!handleAssignments(MIRBuilder, OutArgs, Handler))
9951019
return false;
9961020

1021+
Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1022+
1023+
if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
1024+
TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1025+
MIB.addRegMask(Mask);
1026+
1027+
if (TRI->isAnyArgRegReserved(MF))
1028+
TRI->emitReservedArgRegCallError(MF);
1029+
9971030
// Now we can add the actual call instruction to the correct basic block.
9981031
MIRBuilder.insertInstr(MIB);
9991032

@@ -1011,7 +1044,13 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
10111044
if (!Info.OrigRet.Ty->isVoidTy()) {
10121045
CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
10131046
CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
1014-
if (!handleAssignments(MIRBuilder, InArgs, Handler))
1047+
bool UsingReturnedArg =
1048+
!OutArgs.empty() && OutArgs[0].Flags[0].isReturned();
1049+
ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB,
1050+
RetAssignFn);
1051+
if (!handleAssignments(MIRBuilder, InArgs,
1052+
UsingReturnedArg ? ReturnedArgHandler : Handler,
1053+
UsingReturnedArg ? OutArgs[0].Regs[0] : Register()))
10151054
return false;
10161055
}
10171056

@@ -1033,3 +1072,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
10331072

10341073
return true;
10351074
}
1075+
1076+
bool AArch64CallLowering::isTypeIsValidForThisReturn(EVT Ty) const {
1077+
return Ty.getSizeInBits() == 64;
1078+
}

‎llvm/lib/Target/AArch64/GISel/AArch64CallLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,8 @@ class AArch64CallLowering: public CallLowering {
5555

5656
bool supportSwiftError() const override { return true; }
5757

58+
bool isTypeIsValidForThisReturn(EVT Ty) const override;
59+
5860
private:
5961
using RegHandler = std::function<void(MachineIRBuilder &, Type *, unsigned,
6062
CCValAssign &)>;

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -788,17 +788,17 @@ define void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
788788
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
789789
; CHECK: $x0 = COPY [[COPY]](p0)
790790
; CHECK: $x1 = COPY [[LOAD]](p0)
791-
; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0
792-
; CHECK: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
791+
; CHECK: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
792+
; CHECK: [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
793793
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
794794
; CHECK: G_BR %bb.59
795795
; CHECK: bb.57.bb62:
796796
; CHECK: successors: %bb.59(0x80000000)
797797
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
798798
; CHECK: $x0 = COPY [[COPY]](p0)
799799
; CHECK: $x1 = COPY [[COPY2]](p0)
800-
; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0
801-
; CHECK: [[COPY4:%[0-9]+]]:_(p0) = COPY $x0
800+
; CHECK: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
801+
; CHECK: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
802802
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
803803
; CHECK: G_BR %bb.59
804804
; CHECK: bb.58.bb64:
@@ -812,8 +812,8 @@ define void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
812812
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
813813
; CHECK: $x0 = COPY [[COPY]](p0)
814814
; CHECK: $x1 = COPY [[COPY5]](p0)
815-
; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0
816-
; CHECK: [[COPY6:%[0-9]+]]:_(p0) = COPY $x0
815+
; CHECK: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
816+
; CHECK: [[COPY6:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
817817
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
818818
; CHECK: bb.59.bb68:
819819
; CHECK: RET_ReallyLR

‎llvm/test/CodeGen/AArch64/arm64-this-return.ll

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,7 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
12
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
3+
; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=1 | FileCheck %s
4+
; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=1 -stop-after=irtranslator | FileCheck %s --check-prefix=GISEL-MIR
25

36
%struct.A = type { i8 }
47
%struct.B = type { i32 }
@@ -15,6 +18,19 @@ declare %struct.B* @B_ctor_base_nothisret(%struct.B*, i32)
1518
declare %struct.B* @B_ctor_complete_nothisret(%struct.B*, i32)
1619

1720
define %struct.C* @C_ctor_base(%struct.C* returned %this, i32 %x) {
21+
; GISEL-MIR-LABEL: name: C_ctor_base
22+
; GISEL-MIR: bb.1.entry:
23+
; GISEL-MIR: liveins: $w1, $x0
24+
; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
25+
; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
26+
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
27+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
28+
; GISEL-MIR: BL @A_ctor_base, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0
29+
; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
30+
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
31+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
32+
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
33+
; GISEL-MIR: TCRETURNdi @B_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
1834
entry:
1935
; CHECK-LABEL: C_ctor_base:
2036
; CHECK-NOT: mov {{x[0-9]+}}, x0
@@ -29,6 +45,24 @@ entry:
2945
}
3046

3147
define %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x) {
48+
; GISEL-MIR-LABEL: name: C_ctor_base_nothisret
49+
; GISEL-MIR: bb.1.entry:
50+
; GISEL-MIR: liveins: $w1, $x0
51+
; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
52+
; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
53+
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
54+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
55+
; GISEL-MIR: BL @A_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $x0
56+
; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
57+
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
58+
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
59+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
60+
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
61+
; GISEL-MIR: BL @B_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
62+
; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
63+
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
64+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
65+
; GISEL-MIR: RET_ReallyLR implicit $x0
3266
entry:
3367
; CHECK-LABEL: C_ctor_base_nothisret:
3468
; CHECK: mov [[SAVETHIS:x[0-9]+]], x0
@@ -43,6 +77,14 @@ entry:
4377
}
4478

4579
define %struct.C* @C_ctor_complete(%struct.C* %this, i32 %x) {
80+
; GISEL-MIR-LABEL: name: C_ctor_complete
81+
; GISEL-MIR: bb.1.entry:
82+
; GISEL-MIR: liveins: $w1, $x0
83+
; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
84+
; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
85+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
86+
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
87+
; GISEL-MIR: TCRETURNdi @C_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
4688
entry:
4789
; CHECK-LABEL: C_ctor_complete:
4890
; CHECK: b {{_?C_ctor_base}}
@@ -51,6 +93,19 @@ entry:
5193
}
5294

5395
define %struct.C* @C_ctor_complete_nothisret(%struct.C* %this, i32 %x) {
96+
; GISEL-MIR-LABEL: name: C_ctor_complete_nothisret
97+
; GISEL-MIR: bb.1.entry:
98+
; GISEL-MIR: liveins: $w1, $x0
99+
; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
100+
; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
101+
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
102+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
103+
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
104+
; GISEL-MIR: BL @C_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
105+
; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
106+
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
107+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
108+
; GISEL-MIR: RET_ReallyLR implicit $x0
54109
entry:
55110
; CHECK-LABEL: C_ctor_complete_nothisret:
56111
; CHECK-NOT: b {{_?C_ctor_base_nothisret}}
@@ -59,6 +114,20 @@ entry:
59114
}
60115

61116
define %struct.D* @D_ctor_base(%struct.D* %this, i32 %x) {
117+
; GISEL-MIR-LABEL: name: D_ctor_base
118+
; GISEL-MIR: bb.1.entry:
119+
; GISEL-MIR: liveins: $w1, $x0
120+
; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
121+
; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
122+
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
123+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
124+
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
125+
; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
126+
; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
127+
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
128+
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
129+
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
130+
; GISEL-MIR: TCRETURNdi @B_ctor_complete, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
62131
entry:
63132
; CHECK-LABEL: D_ctor_base:
64133
; CHECK-NOT: mov {{x[0-9]+}}, x0
@@ -72,6 +141,27 @@ entry:
72141
}
73142

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define %struct.E* @E_ctor_base(%struct.E* %this, i32 %x) {
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; GISEL-MIR-LABEL: name: E_ctor_base
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; GISEL-MIR: bb.1.entry:
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; GISEL-MIR: liveins: $w1, $x0
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; GISEL-MIR: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; GISEL-MIR: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; GISEL-MIR: $x0 = COPY [[COPY]](p0)
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; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
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; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
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; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
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; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; GISEL-MIR: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
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; GISEL-MIR: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
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; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; GISEL-MIR: $x0 = COPY [[PTR_ADD]](p0)
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; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
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; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
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; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
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; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; GISEL-MIR: $x0 = COPY [[COPY]](p0)
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; GISEL-MIR: RET_ReallyLR implicit $x0
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entry:
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; CHECK-LABEL: E_ctor_base:
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; CHECK-NOT: b {{_?B_ctor_complete}}

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