Address PR review

Author: farnoy

compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs

@@ -1013,7 +1013,6 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             intrinsic_args!(fx, args => (val, ptr, mask); intrinsic);
 
             let (val_lane_count, val_lane_ty) = val.layout().ty.simd_size_and_type(fx.tcx);
-            // let (ptr, ptr_value) = ptr.try_to_ptr().expect("simd_masked_load ptr");
             let (mask_lane_count, _mask_lane_ty) = mask.layout().ty.simd_size_and_type(fx.tcx);
             let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
             assert_eq!(val_lane_count, mask_lane_count);

compiler/rustc_codegen_llvm/src/intrinsic.rs

@@ -1497,6 +1497,9 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
         // * N: number of elements in the input vectors
         // * T: type of the element to load
         // * M: any integer width is supported, will be truncated to i1
+        // Loads contiguous elements from memory behind `pointer`, but only for
+        // those lanes whose `mask` bit is enabled.
+        // The memory addresses corresponding to the “off” lanes are not accessed.
 
         // The first argument is a passthrough vector providing values for disabled lanes
         let (_, element_ty0) = require_simd!(in_ty, SimdFirst);
@@ -1592,6 +1595,9 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
         // * N: number of elements in the input vectors
         // * T: type of the element to load
         // * M: any integer width is supported, will be truncated to i1
+        // Stores contiguous elements to memory behind `pointer`, but only for
+        // those lanes whose `mask` bit is enabled.
+        // The memory addresses corresponding to the “off” lanes are not accessed.
 
         // The first argument is a passthrough vector providing values for disabled lanes
         let (element_len1, element_ty0) = require_simd!(in_ty, SimdFirst);