Work around stage1 vs. stage2 differences in miri

Author: tgross35

src/tools/miri/tests/panic/mir-validation.rs

@@ -8,6 +8,12 @@
 // Somehow on rustc Windows CI, the "Miri caused an ICE" message is not shown
 // and we don't even get a regular panic; rustc aborts with a different exit code instead.
 //@ignore-host: windows
+
+// FIXME: output is different between stage1 and stage2. This should be possible to remove
+// when stages get bumped.
+// For the grep: cfg(bootstrap)
+//@normalize-stderr-test: "thread 'rustc' panicked" -> "thread 'rustc' ($$HEX) panicked"
+
 #![feature(custom_mir, core_intrinsics)]
 use core::intrinsics::mir::*;
 

src/tools/miri/tests/panic/mir-validation.stderr

@@ -1,5 +1,5 @@
 
-thread 'rustc' panicked at compiler/rustc_mir_transform/src/validate.rs:LL:CC:
+thread 'rustc' ($HEX) panicked at compiler/rustc_mir_transform/src/validate.rs:LL:CC:
 broken MIR in Item(DefId) (after phase change to runtime-optimized) at bb0[1]:
 place (*(_2.0: *mut i32)) has deref as a later projection (it is only permitted as the first projection)
 stack backtrace: