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bjorn3bjorn3
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Sync from rust 65d8785f0a85d233e00fc84445f1aab451ec9f4f
2 parents 2989a25 + c5d0023 commit ebc6ad4

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10 files changed

+25
-66
lines changed

10 files changed

+25
-66
lines changed

‎src/abi.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ impl<'a, 'gcc, 'tcx> AbiBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
1414
// TODO(antoyo)
1515
}
1616

17-
fn get_param(&self, index: usize) -> Self::Value {
17+
fn get_param(&mut self, index: usize) -> Self::Value {
1818
self.cx.current_func.borrow().expect("current func")
1919
.get_param(index as i32)
2020
.to_rvalue()
@@ -48,8 +48,8 @@ impl GccType for CastTarget {
4848
let mut args: Vec<_> = self
4949
.prefix
5050
.iter()
51-
.flat_map(|option_kind| {
52-
option_kind.map(|kind| Reg { kind, size: self.prefix_chunk_size }.gcc_type(cx))
51+
.flat_map(|option_reg| {
52+
option_reg.map(|reg| reg.gcc_type(cx))
5353
})
5454
.chain((0..rest_count).map(|_| rest_gcc_unit))
5555
.collect();

‎src/asm.rs

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,14 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
117117
true
118118
}
119119

120-
fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_operands: &[InlineAsmOperandRef<'tcx, Self>], options: InlineAsmOptions, _span: &[Span], _instance: Instance<'_>) {
120+
fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_operands: &[InlineAsmOperandRef<'tcx, Self>], options: InlineAsmOptions, span: &[Span], _instance: Instance<'_>, _dest_catch_funclet: Option<(Self::BasicBlock, Self::BasicBlock, Option<&Self::Funclet>)>) {
121+
if options.contains(InlineAsmOptions::MAY_UNWIND) {
122+
self.sess()
123+
.struct_span_err(span[0], "GCC backend does not support unwinding from inline asm")
124+
.emit();
125+
return;
126+
}
127+
121128
let asm_arch = self.tcx.sess.asm_arch.unwrap();
122129
let is_x86 = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64);
123130
let att_dialect = is_x86 && options.contains(InlineAsmOptions::ATT_SYNTAX);
@@ -552,7 +559,6 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
552559
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg) => unimplemented!(),
553560
InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => unimplemented!(),
554561
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => unimplemented!(),
555-
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => unimplemented!(),
556562
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
557563
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
558564
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8) => unimplemented!(),
@@ -561,6 +567,7 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
561567
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => unimplemented!(),
562568
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
563569
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => unimplemented!(),
570+
InlineAsmRegClass::Avr(_) => unimplemented!(),
564571
InlineAsmRegClass::Bpf(_) => unimplemented!(),
565572
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => unimplemented!(),
566573
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => unimplemented!(),
@@ -611,8 +618,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
611618
| InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
612619
unimplemented!()
613620
}
614-
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
615-
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => cx.type_i32(),
621+
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)=> cx.type_i32(),
616622
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
617623
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
618624
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
@@ -623,6 +629,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
623629
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
624630
unimplemented!()
625631
}
632+
InlineAsmRegClass::Avr(_) => unimplemented!(),
626633
InlineAsmRegClass::Bpf(_) => unimplemented!(),
627634
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
628635
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
@@ -719,8 +726,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
719726
| InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
720727
unimplemented!()
721728
}
722-
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
723-
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => unimplemented!(),
729+
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => unimplemented!(),
724730
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
725731
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => unimplemented!(),
726732
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
@@ -731,6 +737,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
731737
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
732738
unimplemented!()
733739
}
740+
InlineAsmRegClass::Avr(_) => unimplemented!(),
734741
InlineAsmRegClass::Bpf(_) => unimplemented!(),
735742
InlineAsmRegClass::Hexagon(_) => unimplemented!(),
736743
InlineAsmRegClass::Mips(_) => unimplemented!(),

‎src/back/write.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ pub(crate) unsafe fn codegen(cgcx: &CodegenContext<GccCodegenBackend>, _diag_han
3232
if config.emit_asm {
3333
let _timer = cgcx
3434
.prof
35-
.generic_activity_with_arg("LLVM_module_codegen_emit_asm", &module.name[..]);
35+
.generic_activity_with_arg("LLVM_module_codegen_emit_asm", &*module.name);
3636
let path = cgcx.output_filenames.temp_path(OutputType::Assembly, module_name);
3737
context.compile_to_file(OutputKind::Assembler, path.to_str().expect("path to str"));
3838
}
@@ -41,7 +41,7 @@ pub(crate) unsafe fn codegen(cgcx: &CodegenContext<GccCodegenBackend>, _diag_han
4141
EmitObj::ObjectCode(_) => {
4242
let _timer = cgcx
4343
.prof
44-
.generic_activity_with_arg("LLVM_module_codegen_emit_obj", &module.name[..]);
44+
.generic_activity_with_arg("LLVM_module_codegen_emit_obj", &*module.name);
4545
if env::var("CG_GCCJIT_DUMP_MODULE_NAMES").as_deref() == Ok("1") {
4646
println!("Module {}", module.name);
4747
}

‎src/base.rs

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -135,40 +135,3 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol) -> (Modul
135135

136136
(module, cost)
137137
}
138-
139-
pub fn write_compressed_metadata<'tcx>(tcx: TyCtxt<'tcx>, metadata: &EncodedMetadata, gcc_module: &mut GccContext) {
140-
use snap::write::FrameEncoder;
141-
use std::io::Write;
142-
143-
// Historical note:
144-
//
145-
// When using link.exe it was seen that the section name `.note.rustc`
146-
// was getting shortened to `.note.ru`, and according to the PE and COFF
147-
// specification:
148-
//
149-
// > Executable images do not use a string table and do not support
150-
// > section names longer than 8 characters
151-
//
152-
// https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
153-
//
154-
// As a result, we choose a slightly shorter name! As to why
155-
// `.note.rustc` works on MinGW, see
156-
// https://github.com/llvm/llvm-project/blob/llvmorg-12.0.0/lld/COFF/Writer.cpp#L1190-L1197
157-
let section_name = if tcx.sess.target.is_like_osx { "__DATA,.rustc" } else { ".rustc" };
158-
159-
let context = &gcc_module.context;
160-
let mut compressed = rustc_metadata::METADATA_HEADER.to_vec();
161-
FrameEncoder::new(&mut compressed).write_all(&metadata.raw_data()).unwrap();
162-
163-
let name = exported_symbols::metadata_symbol_name(tcx);
164-
let typ = context.new_array_type(None, context.new_type::<u8>(), compressed.len() as i32);
165-
let global = context.new_global(None, GlobalKind::Exported, typ, name);
166-
global.global_set_initializer(&compressed);
167-
global.set_link_section(section_name);
168-
169-
// Also generate a .section directive to force no
170-
// flags, at least for ELF outputs, so that the
171-
// metadata doesn't get loaded into memory.
172-
let directive = format!(".section {}", section_name);
173-
context.add_top_level_asm(None, &directive);
174-
}

‎src/common.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> {
3232
return value;
3333
}
3434

35-
let global = self.global_string(&*symbol.as_str());
35+
let global = self.global_string(symbol.as_str());
3636

3737
self.const_cstr_cache.borrow_mut().insert(symbol, global);
3838
global

‎src/declare.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> {
1717
global.set_tls_model(self.tls_model);
1818
}
1919
if let Some(link_section) = link_section {
20-
global.set_link_section(&link_section.as_str());
20+
global.set_link_section(link_section.as_str());
2121
}
2222
global
2323
}
@@ -53,7 +53,7 @@ impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> {
5353
global.set_tls_model(self.tls_model);
5454
}
5555
if let Some(link_section) = link_section {
56-
global.set_link_section(&link_section.as_str());
56+
global.set_link_section(link_section.as_str());
5757
}
5858
let global_address = global.get_address(None);
5959
self.globals.borrow_mut().insert(name.to_string(), global_address);

‎src/intrinsic/mod.rs

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
8888
let arg_tys = sig.inputs();
8989
let ret_ty = sig.output();
9090
let name = tcx.item_name(def_id);
91-
let name_str = &*name.as_str();
91+
let name_str = name.as_str();
9292

9393
let llret_ty = self.layout_of(ret_ty).gcc_type(self, true);
9494
let result = PlaceRef::new_sized(llresult, fn_abi.ret.layout);
@@ -316,7 +316,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
316316
extended_asm.add_input_operand(None, "r", result.llval);
317317
extended_asm.add_clobber("memory");
318318
extended_asm.set_volatile_flag(true);
319-
319+
320320
// We have copied the value to `result` already.
321321
return;
322322
}
@@ -363,10 +363,6 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
363363
cond
364364
}
365365

366-
fn sideeffect(&mut self) {
367-
// TODO(antoyo)
368-
}
369-
370366
fn type_test(&mut self, _pointer: Self::Value, _typeid: Self::Value) -> Self::Value {
371367
// Unsupported.
372368
self.context.new_rvalue_from_int(self.int_type, 0)

‎src/intrinsic/simd.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>,
5252
let sig =
5353
tcx.normalize_erasing_late_bound_regions(ty::ParamEnv::reveal_all(), callee_ty.fn_sig(tcx));
5454
let arg_tys = sig.inputs();
55-
let name_str = &*name.as_str();
55+
let name_str = name.as_str();
5656

5757
// every intrinsic below takes a SIMD vector as its first argument
5858
require_simd!(arg_tys[0], "input");

‎src/lib.rs

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@ extern crate rustc_session;
2222
extern crate rustc_span;
2323
extern crate rustc_symbol_mangling;
2424
extern crate rustc_target;
25-
extern crate snap;
2625

2726
// This prevents duplicating functions and statics that are already part of the host rustc process.
2827
#[allow(unused_extern_crates)]
@@ -97,7 +96,7 @@ impl CodegenBackend for GccCodegenBackend {
9796
Box::new(res)
9897
}
9998

100-
fn join_codegen(&self, ongoing_codegen: Box<dyn Any>, sess: &Session) -> Result<(CodegenResults, FxHashMap<WorkProductId, WorkProduct>), ErrorReported> {
99+
fn join_codegen(&self, ongoing_codegen: Box<dyn Any>, sess: &Session, _outputs: &OutputFilenames) -> Result<(CodegenResults, FxHashMap<WorkProductId, WorkProduct>), ErrorReported> {
101100
let (codegen_results, work_products) = ongoing_codegen
102101
.downcast::<rustc_codegen_ssa::back::write::OngoingCodegen<GccCodegenBackend>>()
103102
.expect("Expected GccCodegenBackend's OngoingCodegen, found Box<Any>")
@@ -128,10 +127,6 @@ impl ExtraBackendMethods for GccCodegenBackend {
128127
}
129128
}
130129

131-
fn write_compressed_metadata<'tcx>(&self, tcx: TyCtxt<'tcx>, metadata: &EncodedMetadata, gcc_module: &mut Self::Module) {
132-
base::write_compressed_metadata(tcx, metadata, gcc_module)
133-
}
134-
135130
fn codegen_allocator<'tcx>(&self, tcx: TyCtxt<'tcx>, mods: &mut Self::Module, module_name: &str, kind: AllocatorKind, has_alloc_error_handler: bool) {
136131
unsafe { allocator::codegen(tcx, mods, module_name, kind, has_alloc_error_handler) }
137132
}

‎tests/run/asm.rs

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@
33
// Run-time:
44
// status: 0
55

6-
#![feature(asm, global_asm)]
7-
86
global_asm!("
97
.global add_asm
108
add_asm:

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