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lu-zerognzlbg
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Add Altivec vec_addc
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crates/core_arch/src/powerpc/altivec.rs

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,9 @@ extern "C" {
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fn vsubuhs(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
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#[link_name = "llvm.ppc.altivec.vsubuws"]
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fn vsubuws(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
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#[link_name = "llvm.ppc.altivec.vaddcuw"]
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fn vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;
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}
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macro_rules! s_t_l {
@@ -247,7 +250,7 @@ mod sealed {
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#[inline]
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#[target_feature(enable = "altivec")]
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#[cfg_attr(test, assert_instr($instr))]
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unsafe fn $fun ($($v : $ty),*) -> $r {
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pub unsafe fn $fun ($($v : $ty),*) -> $r {
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$call ($($v),*)
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}
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};
@@ -317,6 +320,8 @@ mod sealed {
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}
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}
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test_impl! { vec_vaddcuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [vaddcuw, vaddcuw] }
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test_impl! { vec_vsubsbs(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vsubsbs, vsubsbs ] }
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test_impl! { vec_vsubshs(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vsubshs, vsubshs ] }
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test_impl! { vec_vsubsws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vsubsws, vsubsws ] }
@@ -1157,6 +1162,13 @@ mod sealed {
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vector_mladd! { vector_signed_short, vector_signed_short, vector_signed_short }
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}
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/// Vector addc.
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#[inline]
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#[target_feature(enable = "altivec")]
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pub unsafe fn vec_addc(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int {
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sealed::vec_vaddcuw(a, b)
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}
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/// Vector abs.
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#[inline]
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#[target_feature(enable = "altivec")]
@@ -1444,6 +1456,8 @@ mod tests {
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}
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}
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test_vec_2! { test_vec_addc, vec_addc, u32x4, [u32::max_value(), 0, 0, 0], [1, 1, 1, 1], [1, 0, 0, 0] }
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macro_rules! test_vec_abs {
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{ $name: ident, $ty: ident, $a: expr, $d: expr } => {
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#[simd_test(enable = "altivec")]

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