@@ -175,6 +175,9 @@ extern "C" {
175
175
fn vsubuhs ( a : vector_unsigned_short , b : vector_unsigned_short ) -> vector_unsigned_short ;
176
176
#[ link_name = "llvm.ppc.altivec.vsubuws" ]
177
177
fn vsubuws ( a : vector_unsigned_int , b : vector_unsigned_int ) -> vector_unsigned_int ;
178
+
179
+ #[ link_name = "llvm.ppc.altivec.vaddcuw" ]
180
+ fn vaddcuw ( a : vector_unsigned_int , b : vector_unsigned_int ) -> vector_unsigned_int ;
178
181
}
179
182
180
183
macro_rules! s_t_l {
@@ -247,7 +250,7 @@ mod sealed {
247
250
#[ inline]
248
251
#[ target_feature( enable = "altivec" ) ]
249
252
#[ cfg_attr( test, assert_instr( $instr) ) ]
250
- unsafe fn $fun ( $( $v : $ty) ,* ) -> $r {
253
+ pub unsafe fn $fun ( $( $v : $ty) ,* ) -> $r {
251
254
$call ( $( $v) ,* )
252
255
}
253
256
} ;
@@ -317,6 +320,8 @@ mod sealed {
317
320
}
318
321
}
319
322
323
+ test_impl ! { vec_vaddcuw( a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int [ vaddcuw, vaddcuw] }
324
+
320
325
test_impl ! { vec_vsubsbs( a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ vsubsbs, vsubsbs ] }
321
326
test_impl ! { vec_vsubshs( a: vector_signed_short, b: vector_signed_short) -> vector_signed_short [ vsubshs, vsubshs ] }
322
327
test_impl ! { vec_vsubsws( a: vector_signed_int, b: vector_signed_int) -> vector_signed_int [ vsubsws, vsubsws ] }
@@ -1157,6 +1162,13 @@ mod sealed {
1157
1162
vector_mladd ! { vector_signed_short, vector_signed_short, vector_signed_short }
1158
1163
}
1159
1164
1165
+ /// Vector addc.
1166
+ #[ inline]
1167
+ #[ target_feature( enable = "altivec" ) ]
1168
+ pub unsafe fn vec_addc ( a : vector_unsigned_int , b : vector_unsigned_int ) -> vector_unsigned_int {
1169
+ sealed:: vec_vaddcuw ( a, b)
1170
+ }
1171
+
1160
1172
/// Vector abs.
1161
1173
#[ inline]
1162
1174
#[ target_feature( enable = "altivec" ) ]
@@ -1444,6 +1456,8 @@ mod tests {
1444
1456
}
1445
1457
}
1446
1458
1459
+ test_vec_2 ! { test_vec_addc, vec_addc, u32x4, [ u32 :: max_value( ) , 0 , 0 , 0 ] , [ 1 , 1 , 1 , 1 ] , [ 1 , 0 , 0 , 0 ] }
1460
+
1447
1461
macro_rules! test_vec_abs {
1448
1462
{ $name: ident, $ty: ident, $a: expr, $d: expr } => {
1449
1463
#[ simd_test( enable = "altivec" ) ]
0 commit comments