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Daniel Smith
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Reference code that is not compiling
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‎crates/core_arch/src/x86/avx512f.rs

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@@ -965,6 +965,185 @@ pub unsafe fn _mm512_set1_epi64(a: i64) -> __m512i {
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transmute(i64x8::splat(a))
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than, and store the results in a mask vector.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_cmplt_ps_mask(a: __m512, b: __m512) -> __mmask16 {
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_mm512_cmp_ps_mask(a, b, _CMP_LT_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than, and store the results in a mask vector k
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/// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmplt_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_mask_cmplt_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
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_mm512_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpgt_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_cmpgt_ps_mask(a: __m512, b: __m512) -> __mmask16 {
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_mm512_cmp_ps_mask(a, b, _CMP_GT_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than, and store the results in a mask vector k
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/// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpgt_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_mask_cmpgt_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
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_mm512_mask_cmp_ps_mask(m, a, b, _CMP_GT_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than-or-equal, and store the results in a mask vector.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmple_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_cmple_ps_mask(a: __m512, b: __m512) -> __mmask16 {
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_mm512_cmp_ps_mask(a, b, _CMP_LE_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than-or-equal, and store the results in a mask vector k
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/// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmple_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_mask_cmple_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
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_mm512_mask_cmp_ps_mask(m, a, b, _CMP_LE_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than-or-equal, and store the results in a mask vector.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpge_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_cmpge_ps_mask(a: __m512, b: __m512) -> __mmask16 {
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_mm512_cmp_ps_mask(a, b, _CMP_LT_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for greater-than-or-equal, and store the results in a mask vector k
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/// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpge_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_mask_cmpge_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
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_mm512_mask_cmp_ps_mask(m, a, b, _CMP_LT_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for equality, and store the results in a mask vector.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpeq_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_cmpeq_ps_mask(a: __m512, b: __m512) -> __mmask16 {
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_mm512_cmp_ps_mask(a, b, _CMP_EQ_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for equality, and store the results in a mask vector k
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/// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpeq_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_mask_cmpeq_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
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_mm512_mask_cmp_ps_mask(m, a, b, _CMP_EQ_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for inequality, and store the results in a mask vector.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmpneq_ps)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_cmpneq_ps_mask(a: __m512, b: __m512) -> __mmask16 {
1080+
_mm512_cmp_ps_mask(a, b, _CMP_NEQ_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b for inequality, and store the results in a mask vector k
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/// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmpneq_ps_mask)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[cfg_attr(test, assert_instr(vcmp))]
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pub unsafe fn _mm512_mask_cmpneq_ps_mask(m: __mmask16, a: __m512, b: __m512) -> __mmask16 {
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_mm512_mask_cmp_ps_mask(m, a, b, _CMP_NEQ_OQ)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b based on the comparison operand specified by op.
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_ps_mask)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[rustc_args_required_const(2)]
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#[cfg_attr(test, assert_instr(vcmp, op = 0))]
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pub unsafe fn _mm512_cmp_ps_mask(a: __m512, b: __m512, op: _MM_CMPINT_ENUM) -> __mmask16 {
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let neg_one = -1;
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macro_rules! call {
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($imm5:expr) => {
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vcmpps(
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a.as_f32x16(),
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b.as_f32x16(),
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$imm5,
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neg_one,
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_MM_FROUND_NINT,
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)
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};
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}
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let r = constify_imm5!(op, call);
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transmute(r)
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}
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/// Compare packed single-precision (32-bit) floating-point elements in a and b based on the comparison operand specified by op,
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/// using zeromask m (elements are zeroed out when the corresponding mask bit is not set).
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///
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,1063&text=_mm512_mask_cmp_ps_mask)
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#[inline]
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#[target_feature(enable = "avx512f")]
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#[rustc_args_required_const(3)]
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#[cfg_attr(test, assert_instr(vcmp, op = 0))]
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pub unsafe fn _mm512_mask_cmp_ps_mask(
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m: __mmask16,
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a: __m512,
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b: __m512,
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op: _MM_CMPINT_ENUM,
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) -> __mmask16 {
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macro_rules! call {
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($imm5:expr) => {
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vcmpps(
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a.as_f32x16(),
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b.as_f32x16(),
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$imm5,
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m as i16,
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_MM_FROUND_NINT,
1140+
)
1141+
};
1142+
}
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let r = constify_imm5!(op, call);
1144+
transmute::<_, __mmask16>(r) & m
1145+
}
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/// Compare packed unsigned 32-bit integers in a and b for less-than, and store the results in a mask vector.
9691148
///
9701149
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_epu32)
@@ -1686,6 +1865,8 @@ extern "C" {
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#[link_name = "llvm.x86.avx512.scatter.qpi.512"]
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fn vpscatterqd(slice: *mut i8, mask: i8, offsets: i64x8, src: i32x8, scale: i32);
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1868+
#[link_name = "llvm.x86.avx512.mask.cmp.ps.512"]
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fn vcmpps(a: f32x16, b: f32x16, op: i32, m: i16, sae: i32) -> i16;
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#[link_name = "llvm.x86.avx512.mask.ucmp.q.512"]
16901871
fn vpcmpuq(a: i64x8, b: i64x8, op: i32, m: i8) -> i8;
16911872
#[link_name = "llvm.x86.avx512.mask.cmp.q.512"]

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