RISC-V: tidying: Make auxvec-based enablement a block

Because this function will be no longer auxvec-only, this commit adds a
comment to mark auxvec-based part.

It *does not* add a comment to "base ISA" part because it may also use
`riscv_hwprobe`-based results.

Author: a4lg

crates/std_detect/src/detect/os/linux/riscv.rs

@@ -19,6 +19,7 @@ pub(crate) fn detect_features() -> cache::Initializer {
         }
     };
 
+    // Use auxiliary vector to enable single-letter ISA extensions and Zicsr.
     // The values are part of the platform-specific [asm/hwcap.h][hwcap]
     //
     // [hwcap]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwcap.h?h=v6.14