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pclmul -> pclmulqdq
1 parent ea70b97 commit 5e08b16

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-5
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2 files changed

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coresimd/src/x86/i686/clmul.rs renamed to coresimd/src/x86/i686/pclmulqdq.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ extern "C" {
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/// The immediate byte is used for determining which halves of `a` and `b`
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/// should be used. Immediate bits other than 0 and 4 are ignored.
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#[inline]
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#[target_feature(enable = "pclmul")]
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#[target_feature(enable = "pclmulqdq")]
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#[cfg_attr(test, assert_instr(pclmulqdq, imm8 = 0))]
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pub unsafe fn _mm_clmulepi64_si128(a: __m128i, b: __m128i, imm8: u8) -> __m128i {
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macro_rules! call {
@@ -42,7 +42,7 @@ mod tests {
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use x86::*;
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#[simd_test = "pclmul"]
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#[simd_test = "pclmulqdq"]
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unsafe fn test_mm_clmulepi64_si128() {
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// Constants taken from https://software.intel.com/sites/default/files/managed/72/cc/clmul-wp-rev-2.02-2014-04-20.pdf
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let a = _mm_set_epi64x(0x7b5b546573745665, 0x63746f725d53475d);

coresimd/x86/i686/mod.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,12 @@
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mod aes;
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pub use self::aes::*;
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mod clmul;
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pub use self::clmul::*;
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mod mmx;
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pub use self::mmx::*;
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mod pclmulqdq;
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pub use self::pclmulqdq::*;
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mod sse;
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pub use self::sse::*;
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