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skip fake instruction asserts
1 parent dbaa61b commit 65e6fcb

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3 files changed

+41
-41
lines changed

3 files changed

+41
-41
lines changed

‎crates/core_arch/src/aarch64/neon/generated.rs

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1707,7 +1707,7 @@ pub unsafe fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t {
17071707
/// Set all vector lanes to the same value
17081708
#[inline]
17091709
#[target_feature(enable = "neon")]
1710-
#[cfg_attr(test, assert_instr(str, N = 0))]
1710+
#[cfg_attr(test, assert_instr(nop, N = 0))]
17111711
#[rustc_legacy_const_generics(1)]
17121712
pub unsafe fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t {
17131713
static_assert!(N : i32 where N == 0);
@@ -1717,7 +1717,7 @@ pub unsafe fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t {
17171717
/// Set all vector lanes to the same value
17181718
#[inline]
17191719
#[target_feature(enable = "neon")]
1720-
#[cfg_attr(test, assert_instr(str, N = 0))]
1720+
#[cfg_attr(test, assert_instr(nop, N = 0))]
17211721
#[rustc_legacy_const_generics(1)]
17221722
pub unsafe fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t {
17231723
static_assert!(N : i32 where N == 0);
@@ -1727,7 +1727,7 @@ pub unsafe fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t {
17271727
/// Set all vector lanes to the same value
17281728
#[inline]
17291729
#[target_feature(enable = "neon")]
1730-
#[cfg_attr(test, assert_instr(str, N = 1))]
1730+
#[cfg_attr(test, assert_instr(nop, N = 1))]
17311731
#[rustc_legacy_const_generics(1)]
17321732
pub unsafe fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
17331733
static_assert_imm1!(N);
@@ -1737,7 +1737,7 @@ pub unsafe fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
17371737
/// Set all vector lanes to the same value
17381738
#[inline]
17391739
#[target_feature(enable = "neon")]
1740-
#[cfg_attr(test, assert_instr(str, N = 1))]
1740+
#[cfg_attr(test, assert_instr(nop, N = 1))]
17411741
#[rustc_legacy_const_generics(1)]
17421742
pub unsafe fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
17431743
static_assert_imm1!(N);
@@ -1747,7 +1747,7 @@ pub unsafe fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
17471747
/// Set all vector lanes to the same value
17481748
#[inline]
17491749
#[target_feature(enable = "neon")]
1750-
#[cfg_attr(test, assert_instr(str, N = 4))]
1750+
#[cfg_attr(test, assert_instr(nop, N = 4))]
17511751
#[rustc_legacy_const_generics(1)]
17521752
pub unsafe fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
17531753
static_assert_imm3!(N);
@@ -1757,7 +1757,7 @@ pub unsafe fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
17571757
/// Set all vector lanes to the same value
17581758
#[inline]
17591759
#[target_feature(enable = "neon")]
1760-
#[cfg_attr(test, assert_instr(str, N = 8))]
1760+
#[cfg_attr(test, assert_instr(nop, N = 8))]
17611761
#[rustc_legacy_const_generics(1)]
17621762
pub unsafe fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
17631763
static_assert_imm4!(N);
@@ -1767,7 +1767,7 @@ pub unsafe fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
17671767
/// Set all vector lanes to the same value
17681768
#[inline]
17691769
#[target_feature(enable = "neon")]
1770-
#[cfg_attr(test, assert_instr(str, N = 2))]
1770+
#[cfg_attr(test, assert_instr(nop, N = 2))]
17711771
#[rustc_legacy_const_generics(1)]
17721772
pub unsafe fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
17731773
static_assert_imm2!(N);
@@ -1777,7 +1777,7 @@ pub unsafe fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
17771777
/// Set all vector lanes to the same value
17781778
#[inline]
17791779
#[target_feature(enable = "neon")]
1780-
#[cfg_attr(test, assert_instr(str, N = 4))]
1780+
#[cfg_attr(test, assert_instr(nop, N = 4))]
17811781
#[rustc_legacy_const_generics(1)]
17821782
pub unsafe fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
17831783
static_assert_imm3!(N);
@@ -1787,7 +1787,7 @@ pub unsafe fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
17871787
/// Set all vector lanes to the same value
17881788
#[inline]
17891789
#[target_feature(enable = "neon")]
1790-
#[cfg_attr(test, assert_instr(str, N = 1))]
1790+
#[cfg_attr(test, assert_instr(nop, N = 1))]
17911791
#[rustc_legacy_const_generics(1)]
17921792
pub unsafe fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
17931793
static_assert_imm1!(N);
@@ -1797,7 +1797,7 @@ pub unsafe fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
17971797
/// Set all vector lanes to the same value
17981798
#[inline]
17991799
#[target_feature(enable = "neon")]
1800-
#[cfg_attr(test, assert_instr(str, N = 2))]
1800+
#[cfg_attr(test, assert_instr(nop, N = 2))]
18011801
#[rustc_legacy_const_generics(1)]
18021802
pub unsafe fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
18031803
static_assert_imm2!(N);
@@ -1807,7 +1807,7 @@ pub unsafe fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
18071807
/// Set all vector lanes to the same value
18081808
#[inline]
18091809
#[target_feature(enable = "neon")]
1810-
#[cfg_attr(test, assert_instr(str, N = 0))]
1810+
#[cfg_attr(test, assert_instr(nop, N = 0))]
18111811
#[rustc_legacy_const_generics(1)]
18121812
pub unsafe fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
18131813
static_assert!(N : i32 where N == 0);
@@ -1817,7 +1817,7 @@ pub unsafe fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
18171817
/// Set all vector lanes to the same value
18181818
#[inline]
18191819
#[target_feature(enable = "neon")]
1820-
#[cfg_attr(test, assert_instr(str, N = 1))]
1820+
#[cfg_attr(test, assert_instr(nop, N = 1))]
18211821
#[rustc_legacy_const_generics(1)]
18221822
pub unsafe fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
18231823
static_assert_imm1!(N);
@@ -1827,7 +1827,7 @@ pub unsafe fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
18271827
/// Set all vector lanes to the same value
18281828
#[inline]
18291829
#[target_feature(enable = "neon")]
1830-
#[cfg_attr(test, assert_instr(str, N = 4))]
1830+
#[cfg_attr(test, assert_instr(nop, N = 4))]
18311831
#[rustc_legacy_const_generics(1)]
18321832
pub unsafe fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
18331833
static_assert_imm3!(N);
@@ -1837,7 +1837,7 @@ pub unsafe fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
18371837
/// Set all vector lanes to the same value
18381838
#[inline]
18391839
#[target_feature(enable = "neon")]
1840-
#[cfg_attr(test, assert_instr(str, N = 8))]
1840+
#[cfg_attr(test, assert_instr(nop, N = 8))]
18411841
#[rustc_legacy_const_generics(1)]
18421842
pub unsafe fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
18431843
static_assert_imm4!(N);
@@ -1847,7 +1847,7 @@ pub unsafe fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
18471847
/// Set all vector lanes to the same value
18481848
#[inline]
18491849
#[target_feature(enable = "neon")]
1850-
#[cfg_attr(test, assert_instr(str, N = 2))]
1850+
#[cfg_attr(test, assert_instr(nop, N = 2))]
18511851
#[rustc_legacy_const_generics(1)]
18521852
pub unsafe fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
18531853
static_assert_imm2!(N);
@@ -1857,7 +1857,7 @@ pub unsafe fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
18571857
/// Set all vector lanes to the same value
18581858
#[inline]
18591859
#[target_feature(enable = "neon")]
1860-
#[cfg_attr(test, assert_instr(str, N = 4))]
1860+
#[cfg_attr(test, assert_instr(nop, N = 4))]
18611861
#[rustc_legacy_const_generics(1)]
18621862
pub unsafe fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
18631863
static_assert_imm3!(N);
@@ -1867,7 +1867,7 @@ pub unsafe fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
18671867
/// Set all vector lanes to the same value
18681868
#[inline]
18691869
#[target_feature(enable = "neon")]
1870-
#[cfg_attr(test, assert_instr(str, N = 1))]
1870+
#[cfg_attr(test, assert_instr(nop, N = 1))]
18711871
#[rustc_legacy_const_generics(1)]
18721872
pub unsafe fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
18731873
static_assert_imm1!(N);
@@ -1877,7 +1877,7 @@ pub unsafe fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
18771877
/// Set all vector lanes to the same value
18781878
#[inline]
18791879
#[target_feature(enable = "neon")]
1880-
#[cfg_attr(test, assert_instr(str, N = 2))]
1880+
#[cfg_attr(test, assert_instr(nop, N = 2))]
18811881
#[rustc_legacy_const_generics(1)]
18821882
pub unsafe fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
18831883
static_assert_imm2!(N);
@@ -1887,7 +1887,7 @@ pub unsafe fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
18871887
/// Set all vector lanes to the same value
18881888
#[inline]
18891889
#[target_feature(enable = "neon")]
1890-
#[cfg_attr(test, assert_instr(str, N = 0))]
1890+
#[cfg_attr(test, assert_instr(nop, N = 0))]
18911891
#[rustc_legacy_const_generics(1)]
18921892
pub unsafe fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
18931893
static_assert!(N : i32 where N == 0);
@@ -1897,7 +1897,7 @@ pub unsafe fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
18971897
/// Set all vector lanes to the same value
18981898
#[inline]
18991899
#[target_feature(enable = "neon")]
1900-
#[cfg_attr(test, assert_instr(str, N = 1))]
1900+
#[cfg_attr(test, assert_instr(nop, N = 1))]
19011901
#[rustc_legacy_const_generics(1)]
19021902
pub unsafe fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
19031903
static_assert_imm1!(N);
@@ -1907,7 +1907,7 @@ pub unsafe fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
19071907
/// Set all vector lanes to the same value
19081908
#[inline]
19091909
#[target_feature(enable = "neon")]
1910-
#[cfg_attr(test, assert_instr(str, N = 4))]
1910+
#[cfg_attr(test, assert_instr(nop, N = 4))]
19111911
#[rustc_legacy_const_generics(1)]
19121912
pub unsafe fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
19131913
static_assert_imm3!(N);
@@ -1917,7 +1917,7 @@ pub unsafe fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
19171917
/// Set all vector lanes to the same value
19181918
#[inline]
19191919
#[target_feature(enable = "neon")]
1920-
#[cfg_attr(test, assert_instr(str, N = 8))]
1920+
#[cfg_attr(test, assert_instr(nop, N = 8))]
19211921
#[rustc_legacy_const_generics(1)]
19221922
pub unsafe fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
19231923
static_assert_imm4!(N);
@@ -1927,7 +1927,7 @@ pub unsafe fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
19271927
/// Set all vector lanes to the same value
19281928
#[inline]
19291929
#[target_feature(enable = "neon")]
1930-
#[cfg_attr(test, assert_instr(str, N = 2))]
1930+
#[cfg_attr(test, assert_instr(nop, N = 2))]
19311931
#[rustc_legacy_const_generics(1)]
19321932
pub unsafe fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 {
19331933
static_assert_imm2!(N);
@@ -1937,7 +1937,7 @@ pub unsafe fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 {
19371937
/// Set all vector lanes to the same value
19381938
#[inline]
19391939
#[target_feature(enable = "neon")]
1940-
#[cfg_attr(test, assert_instr(str, N = 4))]
1940+
#[cfg_attr(test, assert_instr(nop, N = 4))]
19411941
#[rustc_legacy_const_generics(1)]
19421942
pub unsafe fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
19431943
static_assert_imm3!(N);
@@ -1947,7 +1947,7 @@ pub unsafe fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
19471947
/// Set all vector lanes to the same value
19481948
#[inline]
19491949
#[target_feature(enable = "neon")]
1950-
#[cfg_attr(test, assert_instr(str, N = 1))]
1950+
#[cfg_attr(test, assert_instr(nop, N = 1))]
19511951
#[rustc_legacy_const_generics(1)]
19521952
pub unsafe fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
19531953
static_assert_imm1!(N);
@@ -1957,7 +1957,7 @@ pub unsafe fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
19571957
/// Set all vector lanes to the same value
19581958
#[inline]
19591959
#[target_feature(enable = "neon")]
1960-
#[cfg_attr(test, assert_instr(str, N = 2))]
1960+
#[cfg_attr(test, assert_instr(nop, N = 2))]
19611961
#[rustc_legacy_const_generics(1)]
19621962
pub unsafe fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
19631963
static_assert_imm2!(N);
@@ -1967,7 +1967,7 @@ pub unsafe fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
19671967
/// Set all vector lanes to the same value
19681968
#[inline]
19691969
#[target_feature(enable = "neon")]
1970-
#[cfg_attr(test, assert_instr(str, N = 0))]
1970+
#[cfg_attr(test, assert_instr(nop, N = 0))]
19711971
#[rustc_legacy_const_generics(1)]
19721972
pub unsafe fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
19731973
static_assert!(N : i32 where N == 0);
@@ -1977,7 +1977,7 @@ pub unsafe fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
19771977
/// Set all vector lanes to the same value
19781978
#[inline]
19791979
#[target_feature(enable = "neon")]
1980-
#[cfg_attr(test, assert_instr(str, N = 1))]
1980+
#[cfg_attr(test, assert_instr(nop, N = 1))]
19811981
#[rustc_legacy_const_generics(1)]
19821982
pub unsafe fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 {
19831983
static_assert_imm1!(N);

‎crates/core_arch/src/arm/neon/generated.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2528,8 +2528,8 @@ pub unsafe fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
25282528
#[inline]
25292529
#[target_feature(enable = "neon")]
25302530
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2531-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(str, N = 0))]
2532-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(str, N = 0))]
2531+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
2532+
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, N = 0))]
25332533
#[rustc_legacy_const_generics(1)]
25342534
pub unsafe fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
25352535
static_assert!(N : i32 where N == 0);
@@ -2540,8 +2540,8 @@ pub unsafe fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
25402540
#[inline]
25412541
#[target_feature(enable = "neon")]
25422542
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2543-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(str, N = 0))]
2544-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(str, N = 0))]
2543+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
2544+
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, N = 0))]
25452545
#[rustc_legacy_const_generics(1)]
25462546
pub unsafe fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
25472547
static_assert!(N : i32 where N == 0);
@@ -2553,7 +2553,7 @@ pub unsafe fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
25532553
#[target_feature(enable = "neon")]
25542554
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25552555
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
2556-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(str, N = 1))]
2556+
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, N = 1))]
25572557
#[rustc_legacy_const_generics(1)]
25582558
pub unsafe fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
25592559
static_assert_imm1!(N);
@@ -2565,7 +2565,7 @@ pub unsafe fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
25652565
#[target_feature(enable = "neon")]
25662566
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25672567
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
2568-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(str, N = 1))]
2568+
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(nop, N = 1))]
25692569
#[rustc_legacy_const_generics(1)]
25702570
pub unsafe fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
25712571
static_assert_imm1!(N);

‎crates/stdarch-gen/neon.spec

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -956,10 +956,10 @@ a = 0
956956
n = HFLEN
957957
validate 0
958958

959-
aarch64 = str
959+
aarch64 = nop
960960
generate poly64x1_t
961961

962-
arm = str
962+
arm = nop
963963
generate int64x1_t, uint64x1_t
964964

965965
/// Set all vector lanes to the same value
@@ -972,7 +972,7 @@ a = 0.
972972
n = HFLEN
973973
validate 0.
974974

975-
aarch64 = str
975+
aarch64 = nop
976976
generate float64x1_t
977977

978978
/// Set all vector lanes to the same value
@@ -985,7 +985,7 @@ a = 0, 1
985985
n = HFLEN
986986
validate 1
987987

988-
aarch64 = str
988+
aarch64 = nop
989989
generate poly64x2_t:poly64x1_t
990990

991991
arm = vmov
@@ -1001,7 +1001,7 @@ a = 0., 1.
10011001
n = HFLEN
10021002
validate 1.
10031003

1004-
aarch64 = str
1004+
aarch64 = nop
10051005
generate float64x2_t:float64x1_t
10061006

10071007
/// Set all vector lanes to the same value
@@ -1014,7 +1014,7 @@ a = 1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16
10141014
n = HFLEN
10151015
validate 1
10161016

1017-
aarch64 = str
1017+
aarch64 = nop
10181018
generate int8x8_t:i8, int8x16_t:i8, int16x4_t:i16, int16x8_t:i16, int32x2_t:i32, int32x4_t:i32, int64x1_t:i64, int64x2_t:i64
10191019
generate uint8x8_t:u8, uint8x16_t:u8, uint16x4_t:u16, uint16x8_t:u16, uint32x2_t:u32, uint32x4_t:u32, uint64x1_t:u64, uint64x2_t:u64
10201020
generate poly8x8_t:p8, poly8x16_t:p8, poly16x4_t:p16, poly16x8_t:p16
@@ -1029,7 +1029,7 @@ a = 1., 1., 1., 4.
10291029
n = HFLEN
10301030
validate 1.
10311031

1032-
aarch64 = str
1032+
aarch64 = nop
10331033
generate float32x2_t:f32, float32x4_t:f32, float64x1_t:f64, float64x2_t:f64
10341034

10351035
/// Extract vector from pair of vectors

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