RISC-V: Use target_arch for RV(32|64) detection

As Taiki Endo pointed out, there's a problem if we continue using
`target_pointer_width` values to detect an architecture because:

*   There are separate `target_arch`s already and
*   There is an experimental ABI (not ratified though): RV64ILP32.
    cf. <https://lpc.events/event/17/contributions/1475/attachments/1186/2442/rv64ilp32_%20Run%20ILP32%20on%20RV64%20ISA.pdf>

Co-Authored-By: Taiki Endo <[email protected]>

Author: a4lg

crates/std_detect/src/detect/os/linux/riscv.rs

@@ -30,13 +30,15 @@ pub(crate) fn detect_features() -> cache::Initializer {
 
     // Handle base ISA.
     let has_i = bit::test(auxv.hwcap, (b'i' - b'a').into());
-    // If future RV128I is supported, implement with `enable_feature` here
-    #[cfg(target_pointer_width = "64")]
+    // If future RV128I is supported, implement with `enable_feature` here.
+    // Note that we should use `target_arch` instead of `target_pointer_width`
+    // to avoid misdetection caused by experimental ABIs such as RV64ILP32.
+    #[cfg(target_arch = "riscv64")]
     enable_feature(Feature::rv64i, has_i);
-    #[cfg(target_pointer_width = "32")]
+    #[cfg(target_arch = "riscv32")]
     enable_feature(Feature::rv32i, has_i);
     // FIXME: e is not exposed in any of asm/hwcap.h, uapi/asm/hwcap.h, uapi/asm/hwprobe.h
-    #[cfg(target_pointer_width = "32")]
+    #[cfg(target_arch = "riscv32")]
     enable_feature(Feature::rv32e, bit::test(auxv.hwcap, (b'e' - b'a').into()));
 
     // FIXME: Auxvec does not show supervisor feature support, but this mode may be useful