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//!
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//! This CPU feature is available on Intel Broadwell or later CPUs (and some Haswell).
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//!
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+ //! The reference is [Intel 64 and IA-32 Architectures Software Developer's
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+ //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref].
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+ //!
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//! [Uncyclopedia][wikipedia_rtm] provides a quick overview of the assembly instructions, and
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//! Intel's [programming considerations][intel_consid] details what sorts of instructions within a
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//! transaction are likely to cause an abort.
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//!
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+ //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
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//! [wikipedia_rtm]: https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions#Restricted_Transactional_Memory
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//! [intel_consid]: https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-intel-transactional-synchronization-extensions-intel-tsx-programming-considerations
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