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| 1 | +use crate::{ |
| 2 | + core_arch::{simd::*, simd_llvm::*, x86_64::*}, |
| 3 | + mem::{self, transmute}, |
| 4 | +}; |
| 5 | + |
| 6 | +/// Sets packed 64-bit integers in `dst` with the supplied values. |
| 7 | +/// |
| 8 | +/// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909&text=_mm512_set_epi64) |
| 9 | +#[inline] |
| 10 | +#[target_feature(enable = "avx512f")] |
| 11 | +pub unsafe fn _mm512_set_epi64( |
| 12 | + e7: i64, |
| 13 | + e6: i64, |
| 14 | + e5: i64, |
| 15 | + e4: i64, |
| 16 | + e3: i64, |
| 17 | + e2: i64, |
| 18 | + e1: i64, |
| 19 | + e0: i64, |
| 20 | +) -> __m512i { |
| 21 | + let r = i64x8(e0, e1, e2, e3, e4, e5, e6, e7); |
| 22 | + transmute(r) |
| 23 | +} |
| 24 | + |
| 25 | +/// Compare packed unsigned 64-bit integers in a and b for less-than, and store the results in a mask vector. |
| 26 | +/// |
| 27 | +/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_epu64) |
| 28 | +#[inline] |
| 29 | +#[target_feature(enable = "avx512f")] |
| 30 | +#[cfg_attr(test, assert_instr(vpcmpuq))] |
| 31 | +pub unsafe fn _mm512_cmplt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { |
| 32 | + simd_bitmask::<__m512i, _>(simd_lt(a.as_u64x8(), b.as_u64x8())) |
| 33 | +} |
| 34 | + |
| 35 | +#[cfg(test)] |
| 36 | +mod tests { |
| 37 | + use std; |
| 38 | + use stdarch_test::simd_test; |
| 39 | + |
| 40 | + use crate::core_arch::x86::*; |
| 41 | + use crate::core_arch::x86_64::*; |
| 42 | + |
| 43 | + #[simd_test(enable = "avx512f")] |
| 44 | + unsafe fn test_mm512_cmplt_epu64_mask() { |
| 45 | + let a = _mm512_set_epi64(0, 1, -1, u64::MAX as i64, i64::MAX, i64::MIN, 100, -100); |
| 46 | + let b = _mm512_set1_epi64(-1); |
| 47 | + let m = _mm512_cmplt_epu64_mask(a, b); |
| 48 | + assert_eq!(m, 0b11001111); |
| 49 | + } |
| 50 | +} |
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