riscv: adjust documents for virtual memory instructions

Author: luojia65

crates/core_arch/src/riscv/mod.rs

@@ -146,7 +146,7 @@ pub unsafe fn sfence_inval_ir() {
     asm!(".insn i 0x73, 0, x0, x0, 0x181")
 }
 
-/// Loads memory from hypervisor by signed byte integer
+/// Loads virtual machine memory by signed byte integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -163,7 +163,7 @@ pub unsafe fn hlv_b(src: *const i8) -> i8 {
     value
 }
 
-/// Loads memory from hypervisor by unsigned byte integer
+/// Loads virtual machine memory by unsigned byte integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -180,7 +180,7 @@ pub unsafe fn hlv_bu(src: *const u8) -> u8 {
     value
 }
 
-/// Loads memory from hypervisor by signed half integer
+/// Loads virtual machine memory by signed half integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -197,7 +197,7 @@ pub unsafe fn hlv_h(src: *const i16) -> i16 {
     value
 }
 
-/// Loads memory from hypervisor by unsigned half integer
+/// Loads virtual machine memory by unsigned half integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -214,7 +214,7 @@ pub unsafe fn hlv_hu(src: *const u16) -> u16 {
     value
 }
 
-/// Accesses instruction from hypervisor by unsigned half integer
+/// Accesses virtual machine instruction by unsigned half integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// the memory being read must be executable in both stages of address translation,
@@ -231,7 +231,7 @@ pub unsafe fn hlvx_hu(src: *const u16) -> u16 {
     insn
 }
 
-/// Loads memory from hypervisor by signed word integer
+/// Loads virtual machine memory by signed word integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -248,7 +248,7 @@ pub unsafe fn hlv_w(src: *const i32) -> i32 {
     value
 }
 
-/// Accesses instruction from hypervisor by unsigned word integer
+/// Accesses virtual machine instruction by unsigned word integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// the memory being read must be executable in both stages of address translation,
@@ -265,7 +265,7 @@ pub unsafe fn hlvx_wu(src: *const u32) -> u32 {
     insn
 }
 
-/// Stores memory from hypervisor by byte integer
+/// Stores virtual machine memory by byte integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -280,7 +280,7 @@ pub unsafe fn hsv_b(dst: *mut i8, src: i8) {
     asm!(".insn r 0x73, 0x4, 0x31, x0, {}, {}", in(reg) dst, in(reg) src);
 }
 
-/// Stores memory from hypervisor by half integer
+/// Stores virtual machine memory by half integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -295,7 +295,7 @@ pub unsafe fn hsv_h(dst: *mut i16, src: i16) {
     asm!(".insn r 0x73, 0x4, 0x33, x0, {}, {}", in(reg) dst, in(reg) src);
 }
 
-/// Stores memory from hypervisor by word integer
+/// Stores virtual machine memory by word integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory

crates/core_arch/src/riscv64/mod.rs

@@ -1,7 +1,7 @@
 //! RISC-V RV64 specific intrinsics
 use crate::arch::asm;
 
-/// Loads memory from hypervisor by unsigned word integer
+/// Loads virtual machine memory by unsigned word integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -20,7 +20,7 @@ pub unsafe fn hlv_wu(src: *const u32) -> u32 {
     value
 }
 
-/// Loads memory from hypervisor by unsigned double integer
+/// Loads virtual machine memory by unsigned double integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory
@@ -39,7 +39,7 @@ pub unsafe fn hlv_d(src: *const i64) -> i64 {
     value
 }
 
-/// Stores memory from hypervisor by double integer
+/// Stores virtual machine memory by double integer
 ///
 /// This instruction performs an explicit memory access as though `V=1`;
 /// i.e., with the address translation and protection, and the endianness, that apply to memory