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[LLVM][AArch64] Add assembly/disassembly of SVE BFSCALE instruction (llvm#113168)
This patch add assembly/disassembly and tests for sve bfscale instruction according to https://developer.arm.com/documentation/ddi0602 .
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

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@@ -4163,7 +4163,9 @@ defm BFMIN_ZPZZ : sve_fp_2op_p_zds_zeroing_bfloat<int_aarch64_sve_fmin>;
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defm BFMAX_ZPZZ : sve_fp_2op_p_zds_zeroing_bfloat<int_aarch64_sve_fmax>;
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} // HasSVEB16B16, UseExperimentalZeroingPseudos
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let Predicates = [HasSVEBFSCALE] in {
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def BFSCALE_ZPZZ : sve_fp_2op_p_zds_bfscale<0b1001, "bfscale", DestructiveBinary>;
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} // HasSVEBFSCALE
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//===----------------------------------------------------------------------===//
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// SME2.1 or SVE2.1 instructions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

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@@ -2174,6 +2174,11 @@ multiclass sve_fp_2op_p_zds_bfloat<bits<4> opc, string asm, string Ps,
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def : SVE_3_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;
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}
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class sve_fp_2op_p_zds_bfscale<bits<4> opc, string asm, DestructiveInstTypeEnum flags>
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: sve_fp_2op_p_zds<0b00, opc, asm, ZPR16>{
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let DestructiveInstType = flags;
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}
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multiclass sve_fp_2op_p_zds_zeroing_hsd<SDPatternOperator op> {
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def _H_ZERO : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesZero>;
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def _S_ZERO : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesZero>;

‎llvm/test/MC/AArch64/SVE2/bfscale-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-bfscale 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid element width
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bfscale z31.h, p7/m, z31.h, z31.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfscale z31.h, p7/m, z31.h, z31.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfscale z31.h, p7/m, z31.b, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfscale z31.h, p7/m, z31.b, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfscale z31.d, p7/m, z31.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfscale z31.d, p7/m, z31.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Predicate register out of range
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bfscale z31.h, p8/m, z31.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: bfscale z31.h, p8/m, z31.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Destination and source register don't match
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bfscale z31.h, p7/m, z20.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: bfscale z31.h, p7/m, z20.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Using zeroing predicate
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bfscale z0.h, p0/z, z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfscale z0.h, p0/z, z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2/bfscale.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-bfscale < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-bfscale < %s \
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// RUN: | llvm-objdump -d --mattr=+sve,+sve-bfscale - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+sve-bfscale < %s \
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// RUN: | llvm-objdump -d --mattr=-sve-bfscale - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+sve-bfscale < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve,+sve-bfscale -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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bfscale z0.h, p0/m, z0.h, z0.h // 01100101-00001001-10000000-00000000
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// CHECK-INST: bfscale z0.h, p0/m, z0.h, z0.h
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// CHECK-ENCODING: [0x00,0x80,0x09,0x65]
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// CHECK-ERROR: instruction requires: sve-bfscale
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// CHECK-UNKNOWN: 65098000 <unknown>
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bfscale z21.h, p5/m, z21.h, z10.h // 01100101-00001001-10010101-01010101
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// CHECK-INST: bfscale z21.h, p5/m, z21.h, z10.h
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// CHECK-ENCODING: [0x55,0x95,0x09,0x65]
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// CHECK-ERROR: instruction requires: sve-bfscale
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// CHECK-UNKNOWN: 65099555 <unknown>
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bfscale z31.h, p7/m, z31.h, z31.h // 01100101-00001001-10011111-11111111
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// CHECK-INST: bfscale z31.h, p7/m, z31.h, z31.h
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// CHECK-ENCODING: [0xff,0x9f,0x09,0x65]
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// CHECK-ERROR: instruction requires: sve-bfscale
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// CHECK-UNKNOWN: 65099fff <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z23.h, p3/m, z31.h
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bfscale z23.h, p3/m, z23.h, z13.h // 01100101-00001001-10001101-10110111
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// CHECK-INST: movprfx z23.h, p3/m, z31.h
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// CHECK-INST: bfscale z23.h, p3/m, z23.h, z13.h
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// CHECK-ENCODING: [0xb7,0x8d,0x09,0x65]
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// CHECK-ERROR: instruction requires: sve-bfscale
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// CHECK-UNKNOWN: 65098db7 <unknown>
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movprfx z23, z31
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bfscale z23.h, p3/m, z23.h, z13.h // 01100101-00001001-10001101-10110111
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// CHECK-INST: movprfx z23, z31
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// CHECK-INST: bfscale z23.h, p3/m, z23.h, z13.h
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// CHECK-ENCODING: [0xb7,0x8d,0x09,0x65]
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// CHECK-ERROR: instruction requires: sve-bfscale
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// CHECK-UNKNOWN: 65098db7 <unknown>

‎llvm/test/MC/AArch64/SVE2/directive-arch-negative.s

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@@ -29,3 +29,9 @@ rax1 z0.d, z0.d, z0.d
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bgrp z21.s, z10.s, z21.s
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// CHECK: error: instruction requires: sve2-bitperm
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// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
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.arch armv9-a+sve-bfscale
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.arch armv9-a+nosve-bfscale
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bfscale z0.h, p0/m, z0.h, z0.h
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// CHECK: error: instruction requires: sve-bfscale
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// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h

‎llvm/test/MC/AArch64/SVE2/directive-arch.s

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@@ -19,3 +19,7 @@ rax1 z0.d, z0.d, z0.d
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.arch armv9-a+sve2-bitperm
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bgrp z21.s, z10.s, z21.s
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// CHECK: bgrp z21.s, z10.s, z21.s
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.arch armv9-a+sve-bfscale
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bfscale z0.h, p0/m, z0.h, z0.h
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// CHECK: bfscale z0.h, p0/m, z0.h, z0.h

‎llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s

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@@ -29,3 +29,9 @@ rax1 z0.d, z0.d, z0.d
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bgrp z21.s, z10.s, z21.s
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// CHECK: error: instruction requires: sve2-bitperm
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// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
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.arch_extension sve-bfscale
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.arch_extension nosve-bfscale
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bfscale z0.h, p0/m, z0.h, z0.h
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// CHECK: error: instruction requires: sve-bfscale
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// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h

‎llvm/test/MC/AArch64/SVE2/directive-arch_extension.s

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@@ -19,3 +19,7 @@ rax1 z0.d, z0.d, z0.d
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.arch_extension sve2-bitperm
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bgrp z21.s, z10.s, z21.s
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// CHECK: bgrp z21.s, z10.s, z21.s
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.arch_extension sve-bfscale
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bfscale z0.h, p0/m, z0.h, z0.h
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// CHECK: bfscale z0.h, p0/m, z0.h, z0.h

‎llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s

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@@ -29,3 +29,9 @@ rax1 z0.d, z0.d, z0.d
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bgrp z21.s, z10.s, z21.s
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// CHECK: error: instruction requires: sve2-bitperm
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// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
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.cpu generic+sve-bfscale
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.cpu generic+nosve-bfscale
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bfscale z0.h, p0/m, z0.h, z0.h
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// CHECK: error: instruction requires: sve-bfscale
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// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h

‎llvm/test/MC/AArch64/SVE2/directive-cpu.s

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@@ -19,3 +19,7 @@ rax1 z0.d, z0.d, z0.d
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.cpu generic+sve2-bitperm
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bgrp z21.s, z10.s, z21.s
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// CHECK: bgrp z21.s, z10.s, z21.s
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.cpu generic+sve-bfscale
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bfscale z0.h, p0/m, z0.h, z0.h
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// CHECK: bfscale z0.h, p0/m, z0.h, z0.h

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