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Revert "[DXIL] Add GroupMemoryBarrierWithGroupSync intrinsic" (llvm#114322)
Reverts llvm#111884
1 parent ec70cd6 commit 2d6b921

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5 files changed

+22
-209
lines changed

5 files changed

+22
-209
lines changed

‎llvm/include/llvm/IR/IntrinsicsDirectX.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,4 @@ def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, L
9292
def int_dx_splitdouble : DefaultAttrsIntrinsic<[llvm_anyint_ty, LLVMMatchType<0>],
9393
[LLVMScalarOrSameVectorWidth<0, llvm_double_ty>], [IntrNoMem]>;
9494
def int_dx_radians : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
95-
96-
def int_dx_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], []>;
9795
}

‎llvm/lib/Target/DirectX/DXIL.td

Lines changed: 0 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -294,43 +294,6 @@ class Attributes<Version ver = DXIL1_0, list<DXILAttribute> attrs> {
294294
list<DXILAttribute> op_attrs = attrs;
295295
}
296296

297-
class DXILConstant<int value_> {
298-
int value = value_;
299-
}
300-
301-
defset list<DXILConstant> BarrierModes = {
302-
def BarrierMode_DeviceMemoryBarrier : DXILConstant<2>;
303-
def BarrierMode_DeviceMemoryBarrierWithGroupSync : DXILConstant<3>;
304-
def BarrierMode_GroupMemoryBarrier : DXILConstant<8>;
305-
def BarrierMode_GroupMemoryBarrierWithGroupSync : DXILConstant<9>;
306-
def BarrierMode_AllMemoryBarrier : DXILConstant<10>;
307-
def BarrierMode_AllMemoryBarrierWithGroupSync : DXILConstant<11>;
308-
}
309-
310-
// Intrinsic arg selection
311-
class Arg {
312-
int index = -1;
313-
DXILConstant value;
314-
bit is_i8 = 0;
315-
bit is_i32 = 0;
316-
}
317-
class ArgSelect<int index_> : Arg {
318-
let index = index_;
319-
}
320-
class ArgI32<DXILConstant value_> : Arg {
321-
let value = value_;
322-
let is_i32 = 1;
323-
}
324-
class ArgI8<DXILConstant value_> : Arg {
325-
let value = value_;
326-
let is_i8 = 1;
327-
}
328-
329-
class IntrinsicSelect<Intrinsic intrinsic_, list<Arg> args_> {
330-
Intrinsic intrinsic = intrinsic_;
331-
list<Arg> args = args_;
332-
}
333-
334297
// Abstraction DXIL Operation
335298
class DXILOp<int opcode, DXILOpClass opclass> {
336299
// A short description of the operation
@@ -345,9 +308,6 @@ class DXILOp<int opcode, DXILOpClass opclass> {
345308
// LLVM Intrinsic DXIL Operation maps to
346309
Intrinsic LLVMIntrinsic = ?;
347310

348-
// Non-trivial LLVM Intrinsics DXIL Operation maps to
349-
list<IntrinsicSelect> intrinsic_selects = [];
350-
351311
// Result type of the op
352312
DXILOpParamType result;
353313

@@ -869,17 +829,3 @@ def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
869829
let stages = [Stages<DXIL1_0, [all_stages]>];
870830
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
871831
}
872-
873-
def Barrier : DXILOp<80, barrier> {
874-
let Doc = "inserts a memory barrier in the shader";
875-
let intrinsic_selects = [
876-
IntrinsicSelect<
877-
int_dx_group_memory_barrier_with_group_sync,
878-
[ ArgI32<BarrierMode_GroupMemoryBarrierWithGroupSync> ]>,
879-
];
880-
881-
let arguments = [Int32Ty];
882-
let result = VoidTy;
883-
let stages = [Stages<DXIL1_0, [compute, library]>];
884-
let attributes = [Attributes<DXIL1_0, []>];
885-
}

‎llvm/lib/Target/DirectX/DXILOpLowering.cpp

Lines changed: 9 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -106,43 +106,17 @@ class OpLowerer {
106106
return false;
107107
}
108108

109-
struct ArgSelect {
110-
enum class Type {
111-
Index,
112-
I8,
113-
I32,
114-
};
115-
Type Type = Type::Index;
116-
int Value = -1;
117-
};
118-
119-
[[nodiscard]] bool replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp,
120-
ArrayRef<ArgSelect> ArgSelects) {
109+
[[nodiscard]]
110+
bool replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp) {
121111
bool IsVectorArgExpansion = isVectorArgExpansion(F);
122112
return replaceFunction(F, [&](CallInst *CI) -> Error {
123-
OpBuilder.getIRB().SetInsertPoint(CI);
124113
SmallVector<Value *> Args;
125-
if (ArgSelects.size()) {
126-
for (const ArgSelect &A : ArgSelects) {
127-
switch (A.Type) {
128-
case ArgSelect::Type::Index:
129-
Args.push_back(CI->getArgOperand(A.Value));
130-
break;
131-
case ArgSelect::Type::I8:
132-
Args.push_back(OpBuilder.getIRB().getInt8((uint8_t)A.Value));
133-
break;
134-
case ArgSelect::Type::I32:
135-
Args.push_back(OpBuilder.getIRB().getInt32(A.Value));
136-
break;
137-
default:
138-
llvm_unreachable("Invalid type of intrinsic arg select.");
139-
}
140-
}
141-
} else if (IsVectorArgExpansion) {
142-
Args = argVectorFlatten(CI, OpBuilder.getIRB());
143-
} else {
114+
OpBuilder.getIRB().SetInsertPoint(CI);
115+
if (IsVectorArgExpansion) {
116+
SmallVector<Value *> NewArgs = argVectorFlatten(CI, OpBuilder.getIRB());
117+
Args.append(NewArgs.begin(), NewArgs.end());
118+
} else
144119
Args.append(CI->arg_begin(), CI->arg_end());
145-
}
146120

147121
Expected<CallInst *> OpCall =
148122
OpBuilder.tryCreateOp(DXILOp, Args, CI->getName(), F.getReturnType());
@@ -609,10 +583,9 @@ class OpLowerer {
609583
switch (ID) {
610584
default:
611585
continue;
612-
#define DXIL_OP_INTRINSIC(OpCode, Intrin, ...) \
586+
#define DXIL_OP_INTRINSIC(OpCode, Intrin) \
613587
case Intrin: \
614-
HasErrors |= \
615-
replaceFunctionWithOp(F, OpCode, ArrayRef<ArgSelect>{__VA_ARGS__}); \
588+
HasErrors |= replaceFunctionWithOp(F, OpCode); \
616589
break;
617590
#include "DXILOperation.inc"
618591
case Intrinsic::dx_handle_fromBinding:

‎llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll

Lines changed: 0 additions & 8 deletions
This file was deleted.

‎llvm/utils/TableGen/DXILEmitter.cpp

Lines changed: 13 additions & 109 deletions
Original file line numberDiff line numberDiff line change
@@ -32,20 +32,6 @@ using namespace llvm::dxil;
3232

3333
namespace {
3434

35-
struct DXILArgSelect {
36-
enum class Type {
37-
Index,
38-
I32,
39-
I8,
40-
};
41-
Type Type = Type::Index;
42-
int Value = -1;
43-
};
44-
struct DXILIntrinsicSelect {
45-
StringRef Intrinsic;
46-
SmallVector<DXILArgSelect, 4> Args;
47-
};
48-
4935
struct DXILOperationDesc {
5036
std::string OpName; // name of DXIL operation
5137
int OpCode; // ID of DXIL operation
@@ -56,7 +42,8 @@ struct DXILOperationDesc {
5642
SmallVector<const Record *> OverloadRecs;
5743
SmallVector<const Record *> StageRecs;
5844
SmallVector<const Record *> AttrRecs;
59-
SmallVector<DXILIntrinsicSelect> IntrinsicSelects;
45+
StringRef Intrinsic; // The llvm intrinsic map to OpName. Default is "" which
46+
// means no map exists
6047
SmallVector<StringRef, 4>
6148
ShaderStages; // shader stages to which this applies, empty for all.
6249
int OverloadParamIndex; // Index of parameter with overload type.
@@ -84,21 +71,6 @@ static void ascendingSortByVersion(std::vector<const Record *> &Recs) {
8471
});
8572
}
8673

87-
/// Take a `int_{intrinsic_name}` and return just the intrinsic_name part if
88-
/// available. Otherwise return the empty string.
89-
static StringRef GetIntrinsicName(const RecordVal *RV) {
90-
if (RV && RV->getValue()) {
91-
if (const DefInit *DI = dyn_cast<DefInit>(RV->getValue())) {
92-
auto *IntrinsicDef = DI->getDef();
93-
auto DefName = IntrinsicDef->getName();
94-
assert(DefName.starts_with("int_") && "invalid intrinsic name");
95-
// Remove the int_ from intrinsic name.
96-
return DefName.substr(4);
97-
}
98-
}
99-
return "";
100-
}
101-
10274
/// Construct an object using the DXIL Operation records specified
10375
/// in DXIL.td. This serves as the single source of reference of
10476
/// the information extracted from the specified Record R, for
@@ -185,63 +157,14 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
185157
OpName);
186158
}
187159

188-
{
189-
DXILIntrinsicSelect IntrSelect;
190-
IntrSelect.Intrinsic = GetIntrinsicName(R->getValue("LLVMIntrinsic"));
191-
if (IntrSelect.Intrinsic.size())
192-
IntrinsicSelects.emplace_back(std::move(IntrSelect));
193-
}
194-
195-
auto IntrinsicSelectRecords = R->getValueAsListOfDefs("intrinsic_selects");
196-
if (IntrinsicSelectRecords.size()) {
197-
if (IntrinsicSelects.size()) {
198-
PrintFatalError(
199-
R, Twine("LLVMIntrinsic and intrinsic_selects cannot be both "
200-
"defined for DXIL operation - ") +
201-
OpName);
202-
} else {
203-
for (const Record *R : IntrinsicSelectRecords) {
204-
DXILIntrinsicSelect IntrSelect;
205-
IntrSelect.Intrinsic = GetIntrinsicName(R->getValue("intrinsic"));
206-
auto Args = R->getValueAsListOfDefs("args");
207-
for (const Record *Arg : Args) {
208-
bool IsI8 = Arg->getValueAsBit("is_i8");
209-
bool IsI32 = Arg->getValueAsBit("is_i32");
210-
int Index = Arg->getValueAsInt("index");
211-
const Record *ValueRec = Arg->getValueAsOptionalDef("value");
212-
213-
DXILArgSelect ArgSelect;
214-
if (IsI8) {
215-
if (!ValueRec) {
216-
PrintFatalError(R, Twine("'value' must be defined for i8 "
217-
"ArgSelect for DXIL operation - ") +
218-
OpName);
219-
}
220-
ArgSelect.Type = DXILArgSelect::Type::I8;
221-
ArgSelect.Value = ValueRec->getValueAsInt("value");
222-
} else if (IsI32) {
223-
if (!ValueRec) {
224-
PrintFatalError(R, Twine("'value' must be defined for i32 "
225-
"ArgSelect for DXIL operation - ") +
226-
OpName);
227-
}
228-
ArgSelect.Type = DXILArgSelect::Type::I32;
229-
ArgSelect.Value = ValueRec->getValueAsInt("value");
230-
} else {
231-
if (Index < 0) {
232-
PrintFatalError(
233-
R, Twine("Index in ArgSelect<index> must be equal to or "
234-
"greater than 0 for DXIL operation - ") +
235-
OpName);
236-
}
237-
ArgSelect.Type = DXILArgSelect::Type::Index;
238-
ArgSelect.Value = Index;
239-
}
240-
241-
IntrSelect.Args.emplace_back(std::move(ArgSelect));
242-
}
243-
IntrinsicSelects.emplace_back(std::move(IntrSelect));
244-
}
160+
const RecordVal *RV = R->getValue("LLVMIntrinsic");
161+
if (RV && RV->getValue()) {
162+
if (const DefInit *DI = dyn_cast<DefInit>(RV->getValue())) {
163+
auto *IntrinsicDef = DI->getDef();
164+
auto DefName = IntrinsicDef->getName();
165+
assert(DefName.starts_with("int_") && "invalid intrinsic name");
166+
// Remove the int_ from intrinsic name.
167+
Intrinsic = DefName.substr(4);
245168
}
246169
}
247170
}
@@ -454,29 +377,10 @@ static void emitDXILIntrinsicMap(ArrayRef<DXILOperationDesc> Ops,
454377
OS << "#ifdef DXIL_OP_INTRINSIC\n";
455378
OS << "\n";
456379
for (const auto &Op : Ops) {
457-
if (Op.IntrinsicSelects.empty()) {
380+
if (Op.Intrinsic.empty())
458381
continue;
459-
}
460-
for (const DXILIntrinsicSelect &MappedIntr : Op.IntrinsicSelects) {
461-
OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName
462-
<< ", Intrinsic::" << MappedIntr.Intrinsic;
463-
for (const DXILArgSelect &ArgSelect : MappedIntr.Args) {
464-
OS << ", (ArgSelect { ";
465-
switch (ArgSelect.Type) {
466-
case DXILArgSelect::Type::Index:
467-
OS << "ArgSelect::Type::Index, ";
468-
break;
469-
case DXILArgSelect::Type::I8:
470-
OS << "ArgSelect::Type::I8, ";
471-
break;
472-
case DXILArgSelect::Type::I32:
473-
OS << "ArgSelect::Type::I32, ";
474-
break;
475-
}
476-
OS << ArgSelect.Value << "})";
477-
}
478-
OS << ")\n";
479-
}
382+
OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName
383+
<< ", Intrinsic::" << Op.Intrinsic << ")\n";
480384
}
481385
OS << "\n";
482386
OS << "#undef DXIL_OP_INTRINSIC\n";

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