Some fixes after rebasing

Author: thalesfragoso

CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Added DMA support for ADC1.
 - Added type aliases `Tx1` for `Tx<USART1>`, `RxDma1` for `RxDma<USART1, dma1::C5>`, etc.
 - Add ADC1 reading functions for channels 16 (temperature) and 17 (internal reference voltage)
 - Update existing ADC example according to ADC API changes

examples/adc-dma-circ.rs

@@ -27,12 +27,12 @@ fn main() -> ! {
     // clock is configurable. So its frequency may be tweaked to meet certain
     // practical needs. User specified value is be approximated using supported
     // prescaler values 2/4/6/8.
-    let _clocks = rcc.cfgr.adcclk(2.mhz()).freeze(&mut flash.acr);
+    let clocks = rcc.cfgr.adcclk(2.mhz()).freeze(&mut flash.acr);
 
     let dma_ch1 = p.DMA1.split(&mut rcc.ahb).1;
 
     // Setup ADC
-    let adc1 = adc::Adc::adc1(p.ADC1, &mut rcc.apb2);
+    let adc1 = adc::Adc::adc1(p.ADC1, &mut rcc.apb2, clocks.adcclk());
 
     // Setup GPIOA
     let mut gpioa = p.GPIOA.split(&mut rcc.apb2);

examples/adc-dma-rx.rs

@@ -26,12 +26,12 @@ fn main() -> ! {
     // clock is configurable. So its frequency may be tweaked to meet certain
     // practical needs. User specified value is be approximated using supported
     // prescaler values 2/4/6/8.
-    let _clocks = rcc.cfgr.adcclk(2.mhz()).freeze(&mut flash.acr);
+    let clocks = rcc.cfgr.adcclk(2.mhz()).freeze(&mut flash.acr);
 
     let dma_ch1 = p.DMA1.split(&mut rcc.ahb).1;
 
     // Setup ADC
-    let adc1 = adc::Adc::adc1(p.ADC1, &mut rcc.apb2);
+    let adc1 = adc::Adc::adc1(p.ADC1, &mut rcc.apb2, clocks.adcclk());
 
     // Setup GPIOA
     let mut gpioa = p.GPIOA.split(&mut rcc.apb2);

src/adc.rs

@@ -551,8 +551,8 @@ impl<PIN> AdcDma<PIN> where PIN: Channel<ADC1> {
     }
 }
 
-impl<B, PIN> crate::dma::CircReadDma<B, u16> for AdcDma<PIN> 
-where 
+impl<B, PIN> crate::dma::CircReadDma<B, u16> for AdcDma<PIN>
+where
     B: AsMut<[u16]>,
     PIN: Channel<ADC1>,
 {
@@ -582,7 +582,7 @@ where
 }
 
 impl<B, PIN> crate::dma::ReadDma<B, u16> for AdcDma<PIN>
-where 
+where
     B: AsMut<[u16]>,
     PIN: Channel<ADC1>,
 {

src/dma.rs

@@ -286,21 +286,9 @@ macro_rules! dma {
                             })
                         }
 
-                        /// Pauses the transfer
-                        pub fn pause(&mut self) {
-                            self.payload.stop();
-                        }
-
-                        /// Resumes the transfer
-                        pub fn resume(&mut self) {
-                            self.payload.start();
-                        }
-
                         /// Stops the transfer and returns the underlying buffer and RxDma
                         pub fn stop(mut self) -> (&'static mut [B; 2], RxDma<PAYLOAD, $CX>) {
                             self.payload.stop();
-                            self.payload.channel.ifcr().write(|w| w.$ctcifX().set_bit());
-                            self.payload.channel.ifcr().write(|w| w.$chtifX().set_bit());
 
                             (self.buffer, self.payload)
                         }
@@ -332,7 +320,7 @@ macro_rules! dma {
                         }
                     }
 
-                    impl<BUFFER, PAYLOAD, MODE> Transfer<MODE, BUFFER, TxDma<PAYLOAD, $CX>> 
+                    impl<BUFFER, PAYLOAD, MODE> Transfer<MODE, BUFFER, TxDma<PAYLOAD, $CX>>
                     where
                         TxDma<PAYLOAD, $CX>: TransferPayload,
                     {
@@ -358,7 +346,7 @@ macro_rules! dma {
                         }
                     }
 
-                    impl<BUFFER, PAYLOAD> Transfer<W, &'static mut BUFFER, RxDma<PAYLOAD, $CX>> 
+                    impl<BUFFER, PAYLOAD> Transfer<W, &'static mut BUFFER, RxDma<PAYLOAD, $CX>>
                     where
                         RxDma<PAYLOAD, $CX>: TransferPayload,
                     {
@@ -518,4 +506,4 @@ where
     Self: core::marker::Sized,
 {
     fn write(self, buffer: B) -> Transfer<R, B, Self>;
-}
+}

src/rcc.rs

@@ -258,7 +258,7 @@ impl CFGR {
 
         // the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
         // PLL output frequency is a supported one.
-        // usbpre == true: divide clock by 1.5, otherwise no division
+        // usbpre == false: divide clock by 1.5, otherwise no division
         let (usbpre, usbclk_valid) = match (self.hse, pllmul_bits, sysclk) {
             (Some(_), Some(_), 72_000_000) => (false, true),
             (Some(_), Some(_), 48_000_000) => (true, true),

src/serial.rs

@@ -655,4 +655,4 @@ serialdma! {
         dma1::C3,
         dma1::C2,
     ),
-}
+}