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[llvm][ARM] Add Addend Checks for MOVT and MOVW instructions. (llvm#111970)
Previously, any value could be used for the MOVT and MOVW instructions, however the ARM ABI dictates that the addend should be a signed 16 bit value. To ensure this is followed, the Assembler will now check that when using these instructions, the addend is a 16bit signed value, and throw an error if this is not the case. Information relating to the ABI requirements can be found here: https://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst#addends-and-pc-bias-compensation
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‎llvm/docs/ReleaseNotes.md

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@@ -125,6 +125,11 @@ Changes to the ARM Backend
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the required alignment space with a sequence of `0x0` bytes (the requested
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fill value) rather than NOPs.
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* When using the `MOVT` or `MOVW` instructions, the Assembler will now check to
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ensure that any addend that is used is within a 16-bit signed value range. If the
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addend falls outside of this range, the LLVM backend will emit an error like so
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`Relocation Not In Range`.
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Changes to the AVR Backend
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--------------------------
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‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

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@@ -34,6 +34,7 @@
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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@@ -446,6 +447,15 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
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const MCSubtargetInfo* STI) const {
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unsigned Kind = Fixup.getKind();
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// For MOVW/MOVT Instructions, the fixup value must already be 16-bit aligned.
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if ((Kind == ARM::fixup_arm_movw_lo16 || Kind == ARM::fixup_arm_movt_hi16 ||
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Kind == ARM::fixup_t2_movw_lo16 || Kind == ARM::fixup_t2_movt_hi16) &&
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(static_cast<int64_t>(Value) < minIntN(16) ||
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static_cast<int64_t>(Value) > maxIntN(16))) {
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Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
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return 0;
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}
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// MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
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// and .word relocations they put the Thumb bit into the addend if possible.
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// Other relocation types don't want this bit though (branches couldn't encode

‎llvm/test/MC/ARM/Windows/mov32t-range.s

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@@ -21,7 +21,7 @@ truncation:
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.section .rdata,"rd"
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.Lbuffer:
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.zero 65536
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.zero 32767
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.Lerange:
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.asciz "-erange"
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@@ -32,6 +32,6 @@ truncation:
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@ CHECK-RELOCATIONS: }
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@ CHECK-RELOCATIONS: ]
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@ CHECK-ENCODING: 0: f240 0000
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@ CHECK-ENCODING-NEXT: 4: f2c0 0001
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@ CHECK-ENCODING: 0: f647 70ff
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@ CHECK-ENCODING-NEXT: 4: f2c0 0000
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‎llvm/test/MC/ARM/arm-movt-movw-range-fail.s

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@@ -0,0 +1,13 @@
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@RUN: not llvm-mc -triple armv7-eabi -filetype obj -o - %s 2>&1 | FileCheck %s
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.global v
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.text
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movw r1, #:lower16:v + -65536
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movt r1, #:upper16:v + 65536
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@CHECK: error: Relocation Not In Range
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@CHECK: movw r1, #:lower16:v + -65536
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@CHECK: ^
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@CHECK: error: Relocation Not In Range
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@CHECK: movt r1, #:upper16:v + 65536
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@CHECK: ^

‎llvm/test/MC/ARM/arm-movt-movw-range-pass.s

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@RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s 2>&1 | FileCheck %s
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.global v
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.text
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movw r1, #:lower16:v + -20000
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movt r1, #:upper16:v + 20000
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@CHECK-NOT: error: Relocation Not In Range
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@CHECK-NOT: movw r1, #:lower16:v + -20000
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@CHECK-NOT: ^
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@CHECK-NOT: error: Relocation Not In Range
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@CHECK-NOT: movt r1, #:upper16:v + 20000
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@CHECK-NOT: ^

‎llvm/test/MC/ARM/macho-movwt.s

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@@ -8,8 +8,8 @@
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movw r0, :lower16:_x+4
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movt r0, :upper16:_x+4
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movw r0, :lower16:_x+0x10000
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movt r0, :upper16:_x+0x10000
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movw r0, :lower16:_x+0x1000
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movt r0, :upper16:_x+0x1000
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.arm
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movw r0, :lower16:_x
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movw r0, :lower16:_x+4
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movt r0, :upper16:_x+4
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movw r0, :lower16:_x+0x10000
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movt r0, :upper16:_x+0x10000
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movw r0, :lower16:_x+0x1000
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movt r0, :upper16:_x+0x1000
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@ Enter the bizarre world of MachO relocations. First, they're in reverse order
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@ to the actual instructions
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@ Third column identifies ARM/Thumb & HI/LO.
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@ CHECK: 0x2C 0 1 1 ARM_RELOC_HALF 0 _x
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@ CHECK: 0x0 0 1 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x1000 0 1 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x28 0 0 1 ARM_RELOC_HALF 0 _x
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@ CHECK: 0x1 0 0 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x0 0 0 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x24 0 1 1 ARM_RELOC_HALF 0 _x
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@ CHECK: 0x4 0 1 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x0 0 0 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x14 0 3 1 ARM_RELOC_HALF 0 _x
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@ CHECK: 0x0 0 3 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x1000 0 3 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x10 0 2 1 ARM_RELOC_HALF 0 _x
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@ CHECK: 0x1 0 2 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0x0 0 2 0 ARM_RELOC_PAIR 0 -
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@ CHECK: 0xC 0 3 1 ARM_RELOC_HALF 0 _x
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@ CHECK: 0x4 0 3 0 ARM_RELOC_PAIR 0 -

‎llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s

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@@ -11,7 +11,7 @@
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movt r2, :upper16:L1
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movw r12, :lower16:L2
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movt r12, :upper16:L2
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.space 70000
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.space 16382
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.data
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L1: .long 0
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@ CHECK: Section: __data (2)
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@ CHECK: }
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@ CHECK: Relocation {
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@ CHECK: Offset: 0x1184
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@ CHECK: Offset: 0x4012
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@ CHECK: PCRel: 0
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@ CHECK: Length: 3
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@ CHECK: Type: ARM_RELOC_PAIR (1)
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@ CHECK: Section: __data (2)
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@ CHECK: }
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@ CHECK: Relocation {
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@ CHECK: Offset: 0x1
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@ CHECK: Offset: 0x0
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@ CHECK: PCRel: 0
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@ CHECK: Length: 2
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@ CHECK: Type: ARM_RELOC_PAIR (1)
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@ CHECK: Section: __data (2)
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@ CHECK: }
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@ CHECK: Relocation {
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@ CHECK: Offset: 0x1180
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@ CHECK: Offset: 0x400E
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@ CHECK: PCRel: 0
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@ CHECK: Length: 3
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@ CHECK: Type: ARM_RELOC_PAIR (1)
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@ CHECK: Section: __data (2)
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@ CHECK: }
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@ CHECK: Relocation {
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@ CHECK: Offset: 0x1
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@ CHECK: Offset: 0x0
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@ CHECK: PCRel: 0
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@ CHECK: Length: 2
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@ CHECK: Type: ARM_RELOC_PAIR (1)

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