Skip to content

Commit 002f5ab

Browse files
committed
[clang][aarch64] Fix ILP32 ABI for arm_sve_vector_bits
The element types of scalable vectors are defined in terms of stdint types in the ACLE. This patch fixes the mapping to builtin types for the ILP32 ABI when creating VLS types with the arm_sve_vector_bits, where the mapping is as follows: int32_t -> LongTy int64_t -> LongLongTy uint32_t -> UnsignedLongTy uint64_t -> UnsignedLongLongTy This is implemented by leveraging getBuiltinVectorTypeInfo which is target agnostic since it calls ASTContext::getIntTypeForBitwidth for integer types. The element type for svfloat16_t is changed from Float16Ty to HalfTy when creating VLS types since this is what is used elsewhere. For more information, see: https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#types-varying-by-data-model https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-support-for-scalable-vectors Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D87358
1 parent 70a05ee commit 002f5ab

File tree

4 files changed

+14
-30
lines changed

4 files changed

+14
-30
lines changed

clang/lib/AST/ItaniumMangle.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3388,7 +3388,7 @@ void CXXNameMangler::mangleAArch64FixedSveVectorType(const VectorType *T) {
33883388
case BuiltinType::ULong:
33893389
TypeName = "__SVUint64_t";
33903390
break;
3391-
case BuiltinType::Float16:
3391+
case BuiltinType::Half:
33923392
TypeName = "__SVFloat16_t";
33933393
break;
33943394
case BuiltinType::Float:

clang/lib/AST/Type.cpp

Lines changed: 3 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2317,38 +2317,13 @@ QualType Type::getSveEltType(const ASTContext &Ctx) const {
23172317
assert(isVLSTBuiltinType() && "unsupported type!");
23182318

23192319
const BuiltinType *BTy = getAs<BuiltinType>();
2320-
switch (BTy->getKind()) {
2321-
default:
2322-
llvm_unreachable("Unknown builtin SVE type!");
2323-
case BuiltinType::SveInt8:
2324-
return Ctx.SignedCharTy;
2325-
case BuiltinType::SveUint8:
2326-
case BuiltinType::SveBool:
2320+
if (BTy->getKind() == BuiltinType::SveBool)
23272321
// Represent predicates as i8 rather than i1 to avoid any layout issues.
23282322
// The type is bitcasted to a scalable predicate type when casting between
23292323
// scalable and fixed-length vectors.
23302324
return Ctx.UnsignedCharTy;
2331-
case BuiltinType::SveInt16:
2332-
return Ctx.ShortTy;
2333-
case BuiltinType::SveUint16:
2334-
return Ctx.UnsignedShortTy;
2335-
case BuiltinType::SveInt32:
2336-
return Ctx.IntTy;
2337-
case BuiltinType::SveUint32:
2338-
return Ctx.UnsignedIntTy;
2339-
case BuiltinType::SveInt64:
2340-
return Ctx.LongTy;
2341-
case BuiltinType::SveUint64:
2342-
return Ctx.UnsignedLongTy;
2343-
case BuiltinType::SveFloat16:
2344-
return Ctx.Float16Ty;
2345-
case BuiltinType::SveBFloat16:
2346-
return Ctx.BFloat16Ty;
2347-
case BuiltinType::SveFloat32:
2348-
return Ctx.FloatTy;
2349-
case BuiltinType::SveFloat64:
2350-
return Ctx.DoubleTy;
2351-
}
2325+
else
2326+
return Ctx.getBuiltinVectorTypeInfo(BTy).ElementType;
23522327
}
23532328

23542329
bool QualType::isPODType(const ASTContext &Context) const {

clang/lib/CodeGen/TargetInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5627,7 +5627,7 @@ ABIArgInfo AArch64ABIInfo::coerceIllegalVector(QualType Ty) const {
56275627
ResType = llvm::ScalableVectorType::get(
56285628
llvm::Type::getInt64Ty(getVMContext()), 2);
56295629
break;
5630-
case BuiltinType::Float16:
5630+
case BuiltinType::Half:
56315631
ResType = llvm::ScalableVectorType::get(
56325632
llvm::Type::getHalfTy(getVMContext()), 8);
56335633
break;

clang/test/CodeGen/attr-arm-sve-vector-bits-types.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512
55
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=1024 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-1024
66
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=2048 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-2048
7+
// RUN: %clang_cc1 -triple aarch64_32-unknown-darwin -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ILP32
78

89
#include <arm_sve.h>
910

@@ -579,3 +580,11 @@ void f() {
579580
// CHECK-2048-NEXT: %local_arr_f64 = alloca [3 x <32 x double>], align 16
580581
// CHECK-2048-NEXT: %local_arr_bf16 = alloca [3 x <128 x bfloat>], align 16
581582
// CHECK-2048-NEXT: %local_arr_bool = alloca [3 x <32 x i8>], align 2
583+
584+
//===----------------------------------------------------------------------===//
585+
// ILP32 ABI
586+
//===----------------------------------------------------------------------===//
587+
// CHECK-ILP32: @global_i32 = global <16 x i32> zeroinitializer, align 16
588+
// CHECK-ILP32: @global_i64 = global <8 x i64> zeroinitializer, align 16
589+
// CHECK-ILP32: @global_u32 = global <16 x i32> zeroinitializer, align 16
590+
// CHECK-ILP32: @global_u64 = global <8 x i64> zeroinitializer, align 16

0 commit comments

Comments
 (0)