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1 parent 161f64a commit 0078e8fCopy full SHA for 0078e8f
llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
@@ -159,10 +159,10 @@ bool RISCVVMV0Elimination::runOnMachineFunction(MachineFunction &MF) {
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if (MO.isReg() && MO.getReg().isVirtual() &&
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MRI.getRegClass(MO.getReg()) == &RISCV::VMV0RegClass) {
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MRI.recomputeRegClass(MO.getReg());
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- assert(MRI.getRegClass(MO.getReg()) != &RISCV::VMV0RegClass ||
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- MI.isInlineAsm() ||
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- MRI.getVRegDef(MO.getReg())->isInlineAsm() &&
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- "Non-inline-asm use of vmv0 left behind");
+ assert((MRI.getRegClass(MO.getReg()) != &RISCV::VMV0RegClass ||
+ MI.isInlineAsm() ||
+ MRI.getVRegDef(MO.getReg())->isInlineAsm()) &&
+ "Non-inline-asm use of vmv0 left behind");
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}
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