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[RISCV] Split out VSETVLIInfo AVL states to be more explicit (llvm#89964)
We currently use AVLIsReg to represent VLMAX as well as a dummy value for whenever the VL is ignored by vmv.x.s. This splits them out into separate states so that AVLIsReg is always a virtual register and should help with tracking the definition inside VSETVLIInfo directly in llvm#89180. This is almost an NFC but it sets the kill flag for x0 in more places.
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‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 82 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -452,6 +452,8 @@ class VSETVLIInfo {
452452
Uninitialized,
453453
AVLIsReg,
454454
AVLIsImm,
455+
AVLIsVLMAX,
456+
AVLIsIgnored,
455457
Unknown,
456458
} State = Uninitialized;
457459

@@ -478,7 +480,7 @@ class VSETVLIInfo {
478480
bool isUnknown() const { return State == Unknown; }
479481

480482
void setAVLReg(Register Reg) {
481-
assert(Reg.isVirtual() || Reg == RISCV::X0 || Reg == RISCV::NoRegister);
483+
assert(Reg.isVirtual());
482484
AVLReg = Reg;
483485
State = AVLIsReg;
484486
}
@@ -488,8 +490,14 @@ class VSETVLIInfo {
488490
State = AVLIsImm;
489491
}
490492

493+
void setAVLVLMAX() { State = AVLIsVLMAX; }
494+
495+
void setAVLIgnored() { State = AVLIsIgnored; }
496+
491497
bool hasAVLImm() const { return State == AVLIsImm; }
492498
bool hasAVLReg() const { return State == AVLIsReg; }
499+
bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
500+
bool hasAVLIgnored() const { return State == AVLIsIgnored; }
493501
Register getAVLReg() const {
494502
assert(hasAVLReg());
495503
return AVLReg;
@@ -505,6 +513,10 @@ class VSETVLIInfo {
505513
setUnknown();
506514
else if (Info.hasAVLReg())
507515
setAVLReg(Info.getAVLReg());
516+
else if (Info.hasAVLVLMAX())
517+
setAVLVLMAX();
518+
else if (Info.hasAVLIgnored())
519+
setAVLIgnored();
508520
else {
509521
assert(Info.hasAVLImm());
510522
setAVLImm(Info.getAVLImm());
@@ -520,13 +532,14 @@ class VSETVLIInfo {
520532
if (hasAVLImm())
521533
return getAVLImm() > 0;
522534
if (hasAVLReg()) {
523-
if (getAVLReg() == RISCV::X0)
524-
return true;
525-
if (MachineInstr *MI = MRI.getVRegDef(getAVLReg());
526-
MI && isNonZeroLoadImmediate(*MI))
527-
return true;
528-
return false;
535+
MachineInstr *MI = MRI.getUniqueVRegDef(getAVLReg());
536+
assert(MI);
537+
return isNonZeroLoadImmediate(*MI);
529538
}
539+
if (hasAVLVLMAX())
540+
return true;
541+
if (hasAVLIgnored())
542+
return false;
530543
return false;
531544
}
532545

@@ -544,6 +557,12 @@ class VSETVLIInfo {
544557
if (hasAVLImm() && Other.hasAVLImm())
545558
return getAVLImm() == Other.getAVLImm();
546559

560+
if (hasAVLVLMAX())
561+
return Other.hasAVLVLMAX() && hasSameVLMAX(Other);
562+
563+
if (hasAVLIgnored())
564+
return Other.hasAVLIgnored();
565+
547566
return false;
548567
}
549568

@@ -717,6 +736,10 @@ class VSETVLIInfo {
717736
OS << "AVLReg=" << (unsigned)AVLReg;
718737
if (hasAVLImm())
719738
OS << "AVLImm=" << (unsigned)AVLImm;
739+
if (hasAVLVLMAX())
740+
OS << "AVLVLMAX";
741+
if (hasAVLIgnored())
742+
OS << "AVLIgnored";
720743
OS << ", "
721744
<< "VLMul=" << (unsigned)VLMul << ", "
722745
<< "SEW=" << (unsigned)SEW << ", "
@@ -846,7 +869,10 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
846869
Register AVLReg = MI.getOperand(1).getReg();
847870
assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
848871
"Can't handle X0, X0 vsetvli yet");
849-
NewInfo.setAVLReg(AVLReg);
872+
if (AVLReg == RISCV::X0)
873+
NewInfo.setAVLVLMAX();
874+
else
875+
NewInfo.setAVLReg(AVLReg);
850876
}
851877
NewInfo.setVTYPE(MI.getOperand(2).getImm());
852878

@@ -913,7 +939,7 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
913939
if (ST.getRealMinVLen() == ST.getRealMaxVLen() && VLMAX <= 31)
914940
InstrInfo.setAVLImm(VLMAX);
915941
else
916-
InstrInfo.setAVLReg(RISCV::X0);
942+
InstrInfo.setAVLVLMAX();
917943
}
918944
else
919945
InstrInfo.setAVLImm(Imm);
@@ -922,7 +948,10 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
922948
}
923949
} else {
924950
assert(isScalarExtractInstr(MI));
925-
InstrInfo.setAVLReg(RISCV::NoRegister);
951+
// TODO: If we are more clever about x0,x0 insertion then we should be able
952+
// to deduce that the VL is ignored based off of DemandedFields, and remove
953+
// the AVLIsIgnored state. Then we can just use an arbitrary immediate AVL.
954+
InstrInfo.setAVLIgnored();
926955
}
927956
#ifndef NDEBUG
928957
if (std::optional<unsigned> EEW = getEEWForLoadStore(MI)) {
@@ -935,14 +964,14 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
935964
// AVL operand with the AVL of the defining vsetvli. We avoid general
936965
// register AVLs to avoid extending live ranges without being sure we can
937966
// kill the original source reg entirely.
938-
if (InstrInfo.hasAVLReg() && InstrInfo.getAVLReg().isVirtual()) {
939-
MachineInstr *DefMI = MRI->getVRegDef(InstrInfo.getAVLReg());
940-
if (DefMI && isVectorConfigInstr(*DefMI)) {
967+
if (InstrInfo.hasAVLReg()) {
968+
MachineInstr *DefMI = MRI->getUniqueVRegDef(InstrInfo.getAVLReg());
969+
assert(DefMI);
970+
if (isVectorConfigInstr(*DefMI)) {
941971
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
942972
if (DefInstrInfo.hasSameVLMAX(InstrInfo) &&
943-
(DefInstrInfo.hasAVLImm() || DefInstrInfo.getAVLReg() == RISCV::X0)) {
973+
(DefInstrInfo.hasAVLImm() || DefInstrInfo.hasAVLVLMAX()))
944974
InstrInfo.setAVL(DefInstrInfo);
945-
}
946975
}
947976
}
948977

@@ -976,19 +1005,18 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
9761005
// If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
9771006
// it has the same VLMAX we want and the last VL/VTYPE we observed is the
9781007
// same, we can use the X0, X0 form.
979-
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg() &&
980-
Info.getAVLReg().isVirtual()) {
981-
if (MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg())) {
982-
if (isVectorConfigInstr(*DefMI)) {
983-
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
984-
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
985-
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
986-
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
987-
.addReg(RISCV::X0, RegState::Kill)
988-
.addImm(Info.encodeVTYPE())
989-
.addReg(RISCV::VL, RegState::Implicit);
990-
return;
991-
}
1008+
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) {
1009+
MachineInstr *DefMI = MRI->getUniqueVRegDef(Info.getAVLReg());
1010+
assert(DefMI);
1011+
if (isVectorConfigInstr(*DefMI)) {
1012+
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
1013+
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
1014+
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
1015+
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
1016+
.addReg(RISCV::X0, RegState::Kill)
1017+
.addImm(Info.encodeVTYPE())
1018+
.addReg(RISCV::VL, RegState::Implicit);
1019+
return;
9921020
}
9931021
}
9941022
}
@@ -1002,8 +1030,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
10021030
return;
10031031
}
10041032

1005-
Register AVLReg = Info.getAVLReg();
1006-
if (AVLReg == RISCV::NoRegister) {
1033+
if (Info.hasAVLIgnored()) {
10071034
// We can only use x0, x0 if there's no chance of the vtype change causing
10081035
// the previous vl to become invalid.
10091036
if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
@@ -1023,20 +1050,19 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
10231050
return;
10241051
}
10251052

1026-
if (AVLReg.isVirtual())
1027-
MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
1028-
1029-
// Use X0 as the DestReg unless AVLReg is X0. We also need to change the
1030-
// opcode if the AVLReg is X0 as they have different register classes for
1031-
// the AVL operand.
1032-
Register DestReg = RISCV::X0;
1033-
unsigned Opcode = RISCV::PseudoVSETVLI;
1034-
if (AVLReg == RISCV::X0) {
1035-
DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
1036-
Opcode = RISCV::PseudoVSETVLIX0;
1053+
if (Info.hasAVLVLMAX()) {
1054+
Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
1055+
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
1056+
.addReg(DestReg, RegState::Define | RegState::Dead)
1057+
.addReg(RISCV::X0, RegState::Kill)
1058+
.addImm(Info.encodeVTYPE());
1059+
return;
10371060
}
1038-
BuildMI(MBB, InsertPt, DL, TII->get(Opcode))
1039-
.addReg(DestReg, RegState::Define | RegState::Dead)
1061+
1062+
Register AVLReg = Info.getAVLReg();
1063+
MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
1064+
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLI))
1065+
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
10401066
.addReg(AVLReg)
10411067
.addImm(Info.encodeVTYPE());
10421068
}
@@ -1098,14 +1124,13 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
10981124
// it might be defined by a VSET(I)VLI. If it has the same VLMAX we need
10991125
// and the last VL/VTYPE we observed is the same, we don't need a
11001126
// VSETVLI here.
1101-
if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
1102-
CurInfo.hasCompatibleVTYPE(Used, Require)) {
1103-
if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
1104-
if (isVectorConfigInstr(*DefMI)) {
1105-
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
1106-
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
1107-
return false;
1108-
}
1127+
if (Require.hasAVLReg() && CurInfo.hasCompatibleVTYPE(Used, Require)) {
1128+
MachineInstr *DefMI = MRI->getUniqueVRegDef(Require.getAVLReg());
1129+
assert(DefMI);
1130+
if (isVectorConfigInstr(*DefMI)) {
1131+
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
1132+
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
1133+
return false;
11091134
}
11101135
}
11111136

@@ -1290,12 +1315,11 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
12901315
return true;
12911316

12921317
Register AVLReg = Require.getAVLReg();
1293-
if (!AVLReg.isVirtual())
1294-
return true;
12951318

12961319
// We need the AVL to be produce by a PHI node in this basic block.
1297-
MachineInstr *PHI = MRI->getVRegDef(AVLReg);
1298-
if (!PHI || PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB)
1320+
MachineInstr *PHI = MRI->getUniqueVRegDef(AVLReg);
1321+
assert(PHI);
1322+
if (PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB)
12991323
return true;
13001324

13011325
for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
@@ -1463,10 +1487,9 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
14631487
// If the AVL value is a register (other than our VLMAX sentinel),
14641488
// we need to prove the value is available at the point we're going
14651489
// to insert the vsetvli at.
1466-
if (AvailableInfo.hasAVLReg() && RISCV::X0 != AvailableInfo.getAVLReg()) {
1467-
MachineInstr *AVLDefMI = MRI->getVRegDef(AvailableInfo.getAVLReg());
1468-
if (!AVLDefMI)
1469-
return;
1490+
if (AvailableInfo.hasAVLReg()) {
1491+
MachineInstr *AVLDefMI = MRI->getUniqueVRegDef(AvailableInfo.getAVLReg());
1492+
assert(AVLDefMI);
14701493
// This is an inline dominance check which covers the case of
14711494
// UnavailablePred being the preheader of a loop.
14721495
if (AVLDefMI->getParent() != UnavailablePred)

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -517,10 +517,10 @@ body: |
517517
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
518518
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
519519
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
520-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
520+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
521521
; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
522522
; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
523-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
523+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
524524
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 %pt2, 0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
525525
; CHECK-NEXT: {{ $}}
526526
; CHECK-NEXT: bb.1:
@@ -609,7 +609,7 @@ body: |
609609
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
610610
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
611611
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
612-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
612+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
613613
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
614614
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
615615
; CHECK-NEXT: {{ $}}
@@ -681,7 +681,7 @@ body: |
681681
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
682682
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
683683
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
684-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
684+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
685685
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
686686
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
687687
; CHECK-NEXT: {{ $}}
@@ -866,7 +866,7 @@ body: |
866866
; CHECK-NEXT: %t3:vr = COPY $v2
867867
; CHECK-NEXT: %t4:vr = COPY $v3
868868
; CHECK-NEXT: %t5:vrnov0 = COPY $v1
869-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
869+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
870870
; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype
871871
; CHECK-NEXT: PseudoBR %bb.1
872872
; CHECK-NEXT: {{ $}}
@@ -949,7 +949,7 @@ body: |
949949
; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB
950950
; CHECK-NEXT: %inc:gpr = SRLI killed %vlenb, 3
951951
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
952-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
952+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
953953
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
954954
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
955955
; CHECK-NEXT: PseudoBR %bb.1

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,7 @@ body: |
324324
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
325325
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
326326
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)
327-
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
327+
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
328328
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
329329
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
330330
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
@@ -370,7 +370,7 @@ body: |
370370
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
371371
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
372372
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
373-
; CHECK-NEXT: [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
373+
; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
374374
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
375375
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
376376
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
@@ -445,9 +445,9 @@ body: |
445445
; CHECK-NEXT: {{ $}}
446446
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
447447
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
448-
; CHECK-NEXT: [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 %pt, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
448+
; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 %pt, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
449449
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
450-
; CHECK-NEXT: [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 $noreg, 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
450+
; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 $noreg, 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
451451
; CHECK-NEXT: PseudoRET
452452
%pt:vrm2 = IMPLICIT_DEF
453453
%0:vrm2 = PseudoVID_V_M2 %pt, 4, 6, 3
@@ -467,14 +467,14 @@ body: |
467467
; CHECK-NEXT: {{ $}}
468468
; CHECK-NEXT: %cond:gpr = COPY $x10
469469
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
470-
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
470+
; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
471471
; CHECK-NEXT: BEQ %cond, $x0, %bb.2
472472
; CHECK-NEXT: {{ $}}
473473
; CHECK-NEXT: bb.1:
474474
; CHECK-NEXT: successors: %bb.2(0x80000000)
475475
; CHECK-NEXT: {{ $}}
476476
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
477-
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
477+
; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
478478
; CHECK-NEXT: {{ $}}
479479
; CHECK-NEXT: bb.2:
480480
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
@@ -488,8 +488,8 @@ body: |
488488
; CHECK-NEXT: {{ $}}
489489
; CHECK-NEXT: bb.4:
490490
; CHECK-NEXT: $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
491-
; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S $noreg, 5 /* e32 */, implicit $vtype
492-
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
491+
; CHECK-NEXT: dead [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S $noreg, 5 /* e32 */, implicit $vtype
492+
; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
493493
; CHECK-NEXT: PseudoRET
494494
bb.0:
495495
liveins: $x10
@@ -517,10 +517,10 @@ body: |
517517
; CHECK: liveins: $x1
518518
; CHECK-NEXT: {{ $}}
519519
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
520-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $vtype
520+
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $vtype
521521
; CHECK-NEXT: $vl = COPY $x1
522522
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
523-
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
523+
; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
524524
; CHECK-NEXT: PseudoRET
525525
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
526526
%1:gpr = COPY $vtype

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