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[ASan] Changed intrisic implemenation to use PLT safe registers.
Changed registers to R10 and R11 because PLT resolution clobbers them. Also changed the implementation to use R11 instead of RCX, which saves a push/pop. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D115002
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6 files changed

+169
-193
lines changed

6 files changed

+169
-193
lines changed

‎llvm/lib/Target/X86/X86InstrCompiler.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -260,10 +260,10 @@ let isPseudo = 1, SchedRW = [WriteSystem] in {
260260
// Pseudo instructions used by address sanitizer.
261261
//===----------------------------------------------------------------------===//
262262
let
263-
Defs = [R8, EFLAGS] in {
263+
Defs = [R10, R11, EFLAGS] in {
264264
def ASAN_CHECK_MEMACCESS : PseudoI<
265-
(outs), (ins GR64NoR8:$addr, i32imm:$accessinfo),
266-
[(int_asan_check_memaccess GR64NoR8:$addr, (i32 timm:$accessinfo))]>,
265+
(outs), (ins GR64PLTSafe:$addr, i32imm:$accessinfo),
266+
[(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>,
267267
Sched<[]>;
268268
}
269269

‎llvm/lib/Target/X86/X86MCInstLower.cpp

Lines changed: 33 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1359,7 +1359,8 @@ void X86AsmPrinter::emitAsanMemaccessPartial(Module &M, unsigned Reg,
13591359
MCSubtargetInfo &STI) {
13601360
assert(AccessInfo.AccessSizeIndex == 0 || AccessInfo.AccessSizeIndex == 1 ||
13611361
AccessInfo.AccessSizeIndex == 2);
1362-
assert(Reg != X86::R8);
1362+
assert(Reg != X86::R10);
1363+
assert(Reg != X86::R11);
13631364

13641365
uint64_t ShadowBase;
13651366
int MappingScale;
@@ -1368,41 +1369,42 @@ void X86AsmPrinter::emitAsanMemaccessPartial(Module &M, unsigned Reg,
13681369
Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
13691370
AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
13701371

1371-
OutStreamer->emitInstruction(
1372-
MCInstBuilder(X86::MOV64rr).addReg(X86::R8).addReg(X86::NoRegister + Reg),
1373-
STI);
1372+
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
1373+
.addReg(X86::R10)
1374+
.addReg(X86::NoRegister + Reg),
1375+
STI);
13741376
OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
1375-
.addReg(X86::R8)
1376-
.addReg(X86::R8)
1377+
.addReg(X86::R10)
1378+
.addReg(X86::R10)
13771379
.addImm(MappingScale),
13781380
STI);
13791381
if (OrShadowOffset) {
13801382
OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
1381-
.addReg(X86::R8)
1382-
.addReg(X86::R8)
1383+
.addReg(X86::R10)
1384+
.addReg(X86::R10)
13831385
.addImm(ShadowBase),
13841386
STI);
13851387
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV8rm)
1386-
.addReg(X86::R8B)
1387-
.addReg(X86::R8)
1388+
.addReg(X86::R10B)
1389+
.addReg(X86::R10)
13881390
.addImm(1)
13891391
.addReg(X86::NoRegister)
13901392
.addImm(0)
13911393
.addReg(X86::NoRegister),
13921394
STI);
13931395
OutStreamer->emitInstruction(
1394-
MCInstBuilder(X86::TEST8rr).addReg(X86::R8B).addReg(X86::R8B), STI);
1396+
MCInstBuilder(X86::TEST8rr).addReg(X86::R10B).addReg(X86::R10B), STI);
13951397
} else {
13961398
OutStreamer->emitInstruction(MCInstBuilder(X86::MOVSX32rm8)
1397-
.addReg(X86::R8D)
1398-
.addReg(X86::R8)
1399+
.addReg(X86::R10D)
1400+
.addReg(X86::R10)
13991401
.addImm(1)
14001402
.addReg(X86::NoRegister)
14011403
.addImm(ShadowBase)
14021404
.addReg(X86::NoRegister),
14031405
STI);
14041406
OutStreamer->emitInstruction(
1405-
MCInstBuilder(X86::TEST32rr).addReg(X86::R8D).addReg(X86::R8D), STI);
1407+
MCInstBuilder(X86::TEST32rr).addReg(X86::R10D).addReg(X86::R10D), STI);
14061408
}
14071409
MCSymbol *AdditionalCheck = OutContext.createTempSymbol();
14081410
OutStreamer->emitInstruction(
@@ -1416,37 +1418,33 @@ void X86AsmPrinter::emitAsanMemaccessPartial(Module &M, unsigned Reg,
14161418

14171419
// Shadow byte is non-zero so we need to perform additional checks.
14181420
OutStreamer->emitLabel(AdditionalCheck);
1419-
OutStreamer->emitInstruction(MCInstBuilder(X86::PUSH64r).addReg(X86::RCX),
1420-
STI);
14211421
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
1422-
.addReg(X86::RCX)
1422+
.addReg(X86::R11)
14231423
.addReg(X86::NoRegister + Reg),
14241424
STI);
14251425
const size_t Granularity = 1ULL << MappingScale;
14261426
OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8)
14271427
.addReg(X86::NoRegister)
1428-
.addReg(X86::ECX)
1428+
.addReg(X86::R11D)
14291429
.addImm(Granularity - 1),
14301430
STI);
14311431
if (AccessInfo.AccessSizeIndex == 1) {
14321432
OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
14331433
.addReg(X86::NoRegister)
1434-
.addReg(X86::ECX)
1434+
.addReg(X86::R11D)
14351435
.addImm(1),
14361436
STI);
14371437
} else if (AccessInfo.AccessSizeIndex == 2) {
14381438
OutStreamer->emitInstruction(MCInstBuilder(X86::ADD32ri8)
14391439
.addReg(X86::NoRegister)
1440-
.addReg(X86::ECX)
1440+
.addReg(X86::R11D)
14411441
.addImm(3),
14421442
STI);
14431443
}
14441444

14451445
OutStreamer->emitInstruction(
1446-
MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::R8D).addImm(1),
1446+
MCInstBuilder(X86::CMP32rr).addReg(X86::R11D).addReg(X86::R10D).addImm(1),
14471447
STI);
1448-
OutStreamer->emitInstruction(MCInstBuilder(X86::POP64r).addReg(X86::RCX),
1449-
STI);
14501448
OutStreamer->emitInstruction(
14511449
MCInstBuilder(X86::JCC_1)
14521450
.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext))
@@ -1460,7 +1458,8 @@ void X86AsmPrinter::emitAsanMemaccessFull(Module &M, unsigned Reg,
14601458
const ASanAccessInfo &AccessInfo,
14611459
MCSubtargetInfo &STI) {
14621460
assert(AccessInfo.AccessSizeIndex == 3 || AccessInfo.AccessSizeIndex == 4);
1463-
assert(Reg != X86::R8);
1461+
assert(Reg != X86::R10);
1462+
assert(Reg != X86::R11);
14641463

14651464
uint64_t ShadowBase;
14661465
int MappingScale;
@@ -1469,23 +1468,24 @@ void X86AsmPrinter::emitAsanMemaccessFull(Module &M, unsigned Reg,
14691468
Triple(M.getTargetTriple()), M.getDataLayout().getPointerSizeInBits(),
14701469
AccessInfo.CompileKernel, &ShadowBase, &MappingScale, &OrShadowOffset);
14711470

1472-
OutStreamer->emitInstruction(
1473-
MCInstBuilder(X86::MOV64rr).addReg(X86::R8).addReg(X86::NoRegister + Reg),
1474-
STI);
1471+
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
1472+
.addReg(X86::R10)
1473+
.addReg(X86::NoRegister + Reg),
1474+
STI);
14751475
OutStreamer->emitInstruction(MCInstBuilder(X86::SHR64ri)
1476-
.addReg(X86::R8)
1477-
.addReg(X86::R8)
1476+
.addReg(X86::R10)
1477+
.addReg(X86::R10)
14781478
.addImm(MappingScale),
14791479
STI);
14801480
if (OrShadowOffset) {
14811481
OutStreamer->emitInstruction(MCInstBuilder(X86::OR64ri32)
1482-
.addReg(X86::R8)
1483-
.addReg(X86::R8)
1482+
.addReg(X86::R10)
1483+
.addReg(X86::R10)
14841484
.addImm(ShadowBase),
14851485
STI);
14861486
auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
14871487
OutStreamer->emitInstruction(MCInstBuilder(OpCode)
1488-
.addReg(X86::R8)
1488+
.addReg(X86::R10)
14891489
.addImm(1)
14901490
.addReg(X86::NoRegister)
14911491
.addImm(0)
@@ -1495,7 +1495,7 @@ void X86AsmPrinter::emitAsanMemaccessFull(Module &M, unsigned Reg,
14951495
} else {
14961496
auto OpCode = AccessInfo.AccessSizeIndex == 3 ? X86::CMP8mi : X86::CMP16mi8;
14971497
OutStreamer->emitInstruction(MCInstBuilder(OpCode)
1498-
.addReg(X86::R8)
1498+
.addReg(X86::R10)
14991499
.addImm(1)
15001500
.addReg(X86::NoRegister)
15011501
.addImm(ShadowBase)

‎llvm/lib/Target/X86/X86RegisterInfo.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -430,11 +430,11 @@ def GR64 : RegisterClass<"X86", [i64], 64,
430430
(add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
431431
RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
432432

433-
// GR64 - 64-bit GPRs without R8 and RIP. Could be used when emitting code for
434-
// intrinsics, which use implict input registers.
435-
def GR64NoR8 : RegisterClass<"X86", [i64], 64,
436-
(add RAX, RCX, RDX, RSI, RDI, R9, R10, R11,
437-
RBX, R14, R15, R12, R13, RBP, RSP)>;
433+
// GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
434+
// emitting code for intrinsics, which use implict input registers.
435+
def GR64PLTSafe : RegisterClass<"X86", [i64], 64,
436+
(add RAX, RCX, RDX, RSI, RDI, R8, R9,
437+
RBX, R14, R15, R12, R13, RBP)>;
438438

439439
// Segment registers for use by MOV instructions (and others) that have a
440440
// segment register as one operand. Always contain a 16-bit segment

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