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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 |
| 2 | +; RUN: opt -S --passes=slp-vectorizer < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s |
| 3 | + |
| 4 | +define i1 @test(i32 %0, i32 %1, i32 %p) { |
| 5 | +; CHECK-LABEL: define i1 @test( |
| 6 | +; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[P:%.*]]) { |
| 7 | +; CHECK-NEXT: entry: |
| 8 | +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 0 |
| 9 | +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0 |
| 10 | +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer |
| 11 | +; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> zeroinitializer, [[TMP3]] |
| 12 | +; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer |
| 13 | +; CHECK-NEXT: [[CMP6:%.*]] = icmp slt i32 0, [[P]] |
| 14 | +; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]] |
| 15 | +; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]]) |
| 16 | +; CHECK-NEXT: [[OP_RDX:%.*]] = select i1 [[TMP7]], i1 true, i1 [[CMP6]] |
| 17 | +; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP1]] |
| 18 | +; CHECK-NEXT: [[OP_RDX2:%.*]] = select i1 [[OP_RDX]], i1 true, i1 [[OP_RDX1]] |
| 19 | +; CHECK-NEXT: ret i1 [[OP_RDX2]] |
| 20 | +; |
| 21 | +entry: |
| 22 | + %cmp1 = icmp sgt i32 %0, 0 |
| 23 | + %shl1 = shl i32 0, %1 |
| 24 | + %cmp2 = icmp slt i32 %shl1, 0 |
| 25 | + %2 = select i1 %cmp1, i1 true, i1 %cmp2 |
| 26 | + %shl2 = shl i32 0, %1 |
| 27 | + %cmp3 = icmp slt i32 %shl2, 0 |
| 28 | + %3 = select i1 %2, i1 true, i1 %cmp3 |
| 29 | + %shl3 = shl i32 0, %1 |
| 30 | + %cmp4 = icmp slt i32 %shl3, 0 |
| 31 | + %4 = select i1 %3, i1 true, i1 %cmp4 |
| 32 | + %shl4 = shl i32 0, %1 |
| 33 | + %cmp5 = icmp slt i32 %shl4, 0 |
| 34 | + %5 = select i1 %4, i1 true, i1 %cmp5 |
| 35 | + %cmp6 = icmp slt i32 0, %p |
| 36 | + %sel = select i1 %cmp1, i1 true, i1 %cmp6 |
| 37 | + %6 = or i1 %sel, %5 |
| 38 | + ret i1 %6 |
| 39 | +} |
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