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[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
Using the nonans FMF and the DAG.isKnownNeverNaN on the inputs. Reviewed By: fakepaper56 Differential Revision: https://reviews.llvm.org/D156748
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4 files changed

+464
-5
lines changed

4 files changed

+464
-5
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4670,12 +4670,18 @@ static SDValue lowerFMAXIMUM_FMINIMUM(SDValue Op, SelectionDAG &DAG,
46704670
// ensures that when one input is a nan, the other will also be a nan allowing
46714671
// the nan to propagate. If both inputs are nan, this will swap the inputs
46724672
// which is harmless.
4673-
// FIXME: Handle nonans FMF and use isKnownNeverNaN.
4674-
SDValue XIsNonNan = DAG.getSetCC(DL, XLenVT, X, X, ISD::SETOEQ);
4675-
SDValue NewY = DAG.getSelect(DL, VT, XIsNonNan, Y, X);
46764673

4677-
SDValue YIsNonNan = DAG.getSetCC(DL, XLenVT, Y, Y, ISD::SETOEQ);
4678-
SDValue NewX = DAG.getSelect(DL, VT, YIsNonNan, X, Y);
4674+
SDValue NewY = Y;;
4675+
if (!Op->getFlags().hasNoNaNs() && !DAG.isKnownNeverNaN(X)) {
4676+
SDValue XIsNonNan = DAG.getSetCC(DL, XLenVT, X, X, ISD::SETOEQ);
4677+
NewY = DAG.getSelect(DL, VT, XIsNonNan, Y, X);
4678+
}
4679+
4680+
SDValue NewX = X;
4681+
if (!Op->getFlags().hasNoNaNs() && !DAG.isKnownNeverNaN(Y)) {
4682+
SDValue YIsNonNan = DAG.getSetCC(DL, XLenVT, Y, Y, ISD::SETOEQ);
4683+
NewX = DAG.getSelect(DL, VT, YIsNonNan, X, Y);
4684+
}
46794685

46804686
unsigned Opc =
46814687
Op.getOpcode() == ISD::FMAXIMUM ? RISCVISD::FMAX : RISCVISD::FMIN;

‎llvm/test/CodeGen/RISCV/double-maximum-minimum.ll

Lines changed: 203 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,209 @@ define double @fmaximum_f64(double %a, double %b) nounwind {
159159
%1 = call double @llvm.maximum.f64(double %a, double %b)
160160
ret double %1
161161
}
162+
163+
define double @fminimum_nnan_f64(double %a, double %b) nounwind {
164+
; CHECKIFD-LABEL: fminimum_nnan_f64:
165+
; CHECKIFD: # %bb.0:
166+
; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
167+
; CHECKIFD-NEXT: ret
168+
;
169+
; RV32IZFINXZDINX-LABEL: fminimum_nnan_f64:
170+
; RV32IZFINXZDINX: # %bb.0:
171+
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
172+
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
173+
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
174+
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
175+
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
176+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
177+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
178+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
179+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
180+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
181+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
182+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
183+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
184+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
185+
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
186+
; RV32IZFINXZDINX-NEXT: ret
187+
;
188+
; RV64IZFINXZDINX-LABEL: fminimum_nnan_f64:
189+
; RV64IZFINXZDINX: # %bb.0:
190+
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
191+
; RV64IZFINXZDINX-NEXT: ret
192+
%1 = call nnan double @llvm.minimum.f64(double %a, double %b)
193+
ret double %1
194+
}
195+
196+
define double @fmaximum_nnan_f64(double %a, double %b) nounwind {
197+
; CHECKIFD-LABEL: fmaximum_nnan_f64:
198+
; CHECKIFD: # %bb.0:
199+
; CHECKIFD-NEXT: feq.d a0, fa0, fa0
200+
; CHECKIFD-NEXT: fmv.d fa5, fa1
201+
; CHECKIFD-NEXT: beqz a0, .LBB3_3
202+
; CHECKIFD-NEXT: # %bb.1:
203+
; CHECKIFD-NEXT: feq.d a0, fa1, fa1
204+
; CHECKIFD-NEXT: beqz a0, .LBB3_4
205+
; CHECKIFD-NEXT: .LBB3_2:
206+
; CHECKIFD-NEXT: fmin.d fa0, fa0, fa5
207+
; CHECKIFD-NEXT: ret
208+
; CHECKIFD-NEXT: .LBB3_3:
209+
; CHECKIFD-NEXT: fmv.d fa5, fa0
210+
; CHECKIFD-NEXT: feq.d a0, fa1, fa1
211+
; CHECKIFD-NEXT: bnez a0, .LBB3_2
212+
; CHECKIFD-NEXT: .LBB3_4:
213+
; CHECKIFD-NEXT: fmin.d fa0, fa1, fa5
214+
; CHECKIFD-NEXT: ret
215+
;
216+
; RV32IZFINXZDINX-LABEL: fmaximum_nnan_f64:
217+
; RV32IZFINXZDINX: # %bb.0:
218+
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
219+
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
220+
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
221+
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
222+
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
223+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
224+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
225+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
226+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
227+
; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
228+
; RV32IZFINXZDINX-NEXT: mv a4, a2
229+
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_2
230+
; RV32IZFINXZDINX-NEXT: # %bb.1:
231+
; RV32IZFINXZDINX-NEXT: mv a4, a0
232+
; RV32IZFINXZDINX-NEXT: .LBB3_2:
233+
; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
234+
; RV32IZFINXZDINX-NEXT: bnez a6, .LBB3_4
235+
; RV32IZFINXZDINX-NEXT: # %bb.3:
236+
; RV32IZFINXZDINX-NEXT: mv a0, a2
237+
; RV32IZFINXZDINX-NEXT: .LBB3_4:
238+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
239+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
240+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
241+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
242+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
243+
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
244+
; RV32IZFINXZDINX-NEXT: ret
245+
;
246+
; RV64IZFINXZDINX-LABEL: fmaximum_nnan_f64:
247+
; RV64IZFINXZDINX: # %bb.0:
248+
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
249+
; RV64IZFINXZDINX-NEXT: mv a2, a1
250+
; RV64IZFINXZDINX-NEXT: beqz a3, .LBB3_3
251+
; RV64IZFINXZDINX-NEXT: # %bb.1:
252+
; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
253+
; RV64IZFINXZDINX-NEXT: beqz a3, .LBB3_4
254+
; RV64IZFINXZDINX-NEXT: .LBB3_2:
255+
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
256+
; RV64IZFINXZDINX-NEXT: ret
257+
; RV64IZFINXZDINX-NEXT: .LBB3_3:
258+
; RV64IZFINXZDINX-NEXT: mv a2, a0
259+
; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
260+
; RV64IZFINXZDINX-NEXT: bnez a3, .LBB3_2
261+
; RV64IZFINXZDINX-NEXT: .LBB3_4:
262+
; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a2
263+
; RV64IZFINXZDINX-NEXT: ret
264+
%1 = call double @llvm.minimum.f64(double %a, double %b)
265+
ret double %1
266+
}
267+
268+
define double @fminimum_nnan_op_f64(double %a, double %b) nounwind {
269+
; CHECKIFD-LABEL: fminimum_nnan_op_f64:
270+
; CHECKIFD: # %bb.0:
271+
; CHECKIFD-NEXT: feq.d a0, fa1, fa1
272+
; CHECKIFD-NEXT: bnez a0, .LBB4_2
273+
; CHECKIFD-NEXT: # %bb.1:
274+
; CHECKIFD-NEXT: fmin.d fa0, fa1, fa1
275+
; CHECKIFD-NEXT: ret
276+
; CHECKIFD-NEXT: .LBB4_2:
277+
; CHECKIFD-NEXT: fadd.d fa5, fa0, fa0
278+
; CHECKIFD-NEXT: fmin.d fa0, fa5, fa1
279+
; CHECKIFD-NEXT: ret
280+
;
281+
; RV32IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
282+
; RV32IZFINXZDINX: # %bb.0:
283+
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
284+
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
285+
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
286+
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
287+
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
288+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
289+
; RV32IZFINXZDINX-NEXT: feq.d a0, a2, a2
290+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
291+
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB4_2
292+
; RV32IZFINXZDINX-NEXT: # %bb.1:
293+
; RV32IZFINXZDINX-NEXT: mv a0, a2
294+
; RV32IZFINXZDINX-NEXT: j .LBB4_3
295+
; RV32IZFINXZDINX-NEXT: .LBB4_2:
296+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
297+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
298+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a0
299+
; RV32IZFINXZDINX-NEXT: .LBB4_3:
300+
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
301+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
302+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
303+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
304+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
305+
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
306+
; RV32IZFINXZDINX-NEXT: ret
307+
;
308+
; RV64IZFINXZDINX-LABEL: fminimum_nnan_op_f64:
309+
; RV64IZFINXZDINX: # %bb.0:
310+
; RV64IZFINXZDINX-NEXT: feq.d a2, a1, a1
311+
; RV64IZFINXZDINX-NEXT: bnez a2, .LBB4_2
312+
; RV64IZFINXZDINX-NEXT: # %bb.1:
313+
; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a1
314+
; RV64IZFINXZDINX-NEXT: ret
315+
; RV64IZFINXZDINX-NEXT: .LBB4_2:
316+
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a0
317+
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
318+
; RV64IZFINXZDINX-NEXT: ret
319+
%c = fadd nnan double %a, %a
320+
%1 = call double @llvm.minimum.f64(double %c, double %b)
321+
ret double %1
322+
}
323+
324+
define double @fmaximum_nnan_op_f64(double %a, double %b) nounwind {
325+
; CHECKIFD-LABEL: fmaximum_nnan_op_f64:
326+
; CHECKIFD: # %bb.0:
327+
; CHECKIFD-NEXT: fadd.d fa5, fa0, fa1
328+
; CHECKIFD-NEXT: fsub.d fa4, fa0, fa1
329+
; CHECKIFD-NEXT: fmax.d fa0, fa5, fa4
330+
; CHECKIFD-NEXT: ret
331+
;
332+
; RV32IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
333+
; RV32IZFINXZDINX: # %bb.0:
334+
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
335+
; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
336+
; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
337+
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
338+
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
339+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
340+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
341+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
342+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
343+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a0, a2
344+
; RV32IZFINXZDINX-NEXT: fsub.d a0, a0, a2
345+
; RV32IZFINXZDINX-NEXT: fmax.d a0, a4, a0
346+
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
347+
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
348+
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
349+
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
350+
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
351+
; RV32IZFINXZDINX-NEXT: ret
352+
;
353+
; RV64IZFINXZDINX-LABEL: fmaximum_nnan_op_f64:
354+
; RV64IZFINXZDINX: # %bb.0:
355+
; RV64IZFINXZDINX-NEXT: fadd.d a2, a0, a1
356+
; RV64IZFINXZDINX-NEXT: fsub.d a0, a0, a1
357+
; RV64IZFINXZDINX-NEXT: fmax.d a0, a2, a0
358+
; RV64IZFINXZDINX-NEXT: ret
359+
%c = fadd nnan double %a, %b
360+
%d = fsub nnan double %a, %b
361+
%1 = call double @llvm.maximum.f64(double %c, double %d)
362+
ret double %1
363+
}
364+
162365
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
163366
; RV32IFD: {{.*}}
164367
; RV64IFD: {{.*}}

‎llvm/test/CodeGen/RISCV/float-maximum-minimum.ll

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -181,3 +181,162 @@ define float @fmaximum_f32(float %a, float %b) nounwind {
181181
%1 = call float @llvm.maximum.f32(float %a, float %b)
182182
ret float %1
183183
}
184+
185+
define float @fminimum_nnan_f32(float %a, float %b) nounwind {
186+
; RV32IF-LABEL: fminimum_nnan_f32:
187+
; RV32IF: # %bb.0:
188+
; RV32IF-NEXT: fmin.s fa0, fa0, fa1
189+
; RV32IF-NEXT: ret
190+
;
191+
; RV32IZFINX-LABEL: fminimum_nnan_f32:
192+
; RV32IZFINX: # %bb.0:
193+
; RV32IZFINX-NEXT: fmin.s a0, a0, a1
194+
; RV32IZFINX-NEXT: ret
195+
;
196+
; RV64IF-LABEL: fminimum_nnan_f32:
197+
; RV64IF: # %bb.0:
198+
; RV64IF-NEXT: fmin.s fa0, fa0, fa1
199+
; RV64IF-NEXT: ret
200+
;
201+
; RV64IZFINX-LABEL: fminimum_nnan_f32:
202+
; RV64IZFINX: # %bb.0:
203+
; RV64IZFINX-NEXT: fmin.s a0, a0, a1
204+
; RV64IZFINX-NEXT: ret
205+
%1 = call nnan float @llvm.minimum.f32(float %a, float %b)
206+
ret float %1
207+
}
208+
209+
define float @fmaximum_nnan_f32(float %a, float %b) nounwind {
210+
; RV32IF-LABEL: fmaximum_nnan_f32:
211+
; RV32IF: # %bb.0:
212+
; RV32IF-NEXT: fmax.s fa0, fa0, fa1
213+
; RV32IF-NEXT: ret
214+
;
215+
; RV32IZFINX-LABEL: fmaximum_nnan_f32:
216+
; RV32IZFINX: # %bb.0:
217+
; RV32IZFINX-NEXT: fmax.s a0, a0, a1
218+
; RV32IZFINX-NEXT: ret
219+
;
220+
; RV64IF-LABEL: fmaximum_nnan_f32:
221+
; RV64IF: # %bb.0:
222+
; RV64IF-NEXT: fmax.s fa0, fa0, fa1
223+
; RV64IF-NEXT: ret
224+
;
225+
; RV64IZFINX-LABEL: fmaximum_nnan_f32:
226+
; RV64IZFINX: # %bb.0:
227+
; RV64IZFINX-NEXT: fmax.s a0, a0, a1
228+
; RV64IZFINX-NEXT: ret
229+
%1 = call nnan float @llvm.maximum.f32(float %a, float %b)
230+
ret float %1
231+
}
232+
233+
define float @fminimum_nnan_attr_f32(float %a, float %b) nounwind "no-nans-fp-math"="true" {
234+
; RV32IF-LABEL: fminimum_nnan_attr_f32:
235+
; RV32IF: # %bb.0:
236+
; RV32IF-NEXT: fmin.s fa0, fa0, fa1
237+
; RV32IF-NEXT: ret
238+
;
239+
; RV32IZFINX-LABEL: fminimum_nnan_attr_f32:
240+
; RV32IZFINX: # %bb.0:
241+
; RV32IZFINX-NEXT: fmin.s a0, a0, a1
242+
; RV32IZFINX-NEXT: ret
243+
;
244+
; RV64IF-LABEL: fminimum_nnan_attr_f32:
245+
; RV64IF: # %bb.0:
246+
; RV64IF-NEXT: fmin.s fa0, fa0, fa1
247+
; RV64IF-NEXT: ret
248+
;
249+
; RV64IZFINX-LABEL: fminimum_nnan_attr_f32:
250+
; RV64IZFINX: # %bb.0:
251+
; RV64IZFINX-NEXT: fmin.s a0, a0, a1
252+
; RV64IZFINX-NEXT: ret
253+
%1 = call float @llvm.minimum.f32(float %a, float %b)
254+
ret float %1
255+
}
256+
257+
define float @fminimum_nnan_op_f32(float %a, float %b) nounwind {
258+
; RV32IF-LABEL: fminimum_nnan_op_f32:
259+
; RV32IF: # %bb.0:
260+
; RV32IF-NEXT: feq.s a0, fa0, fa0
261+
; RV32IF-NEXT: bnez a0, .LBB5_2
262+
; RV32IF-NEXT: # %bb.1:
263+
; RV32IF-NEXT: fmin.s fa0, fa0, fa0
264+
; RV32IF-NEXT: ret
265+
; RV32IF-NEXT: .LBB5_2:
266+
; RV32IF-NEXT: fadd.s fa5, fa0, fa0
267+
; RV32IF-NEXT: fmin.s fa0, fa0, fa5
268+
; RV32IF-NEXT: ret
269+
;
270+
; RV32IZFINX-LABEL: fminimum_nnan_op_f32:
271+
; RV32IZFINX: # %bb.0:
272+
; RV32IZFINX-NEXT: feq.s a1, a0, a0
273+
; RV32IZFINX-NEXT: bnez a1, .LBB5_2
274+
; RV32IZFINX-NEXT: # %bb.1:
275+
; RV32IZFINX-NEXT: fmin.s a0, a0, a0
276+
; RV32IZFINX-NEXT: ret
277+
; RV32IZFINX-NEXT: .LBB5_2:
278+
; RV32IZFINX-NEXT: fadd.s a1, a0, a0
279+
; RV32IZFINX-NEXT: fmin.s a0, a0, a1
280+
; RV32IZFINX-NEXT: ret
281+
;
282+
; RV64IF-LABEL: fminimum_nnan_op_f32:
283+
; RV64IF: # %bb.0:
284+
; RV64IF-NEXT: feq.s a0, fa0, fa0
285+
; RV64IF-NEXT: bnez a0, .LBB5_2
286+
; RV64IF-NEXT: # %bb.1:
287+
; RV64IF-NEXT: fmin.s fa0, fa0, fa0
288+
; RV64IF-NEXT: ret
289+
; RV64IF-NEXT: .LBB5_2:
290+
; RV64IF-NEXT: fadd.s fa5, fa0, fa0
291+
; RV64IF-NEXT: fmin.s fa0, fa0, fa5
292+
; RV64IF-NEXT: ret
293+
;
294+
; RV64IZFINX-LABEL: fminimum_nnan_op_f32:
295+
; RV64IZFINX: # %bb.0:
296+
; RV64IZFINX-NEXT: feq.s a1, a0, a0
297+
; RV64IZFINX-NEXT: bnez a1, .LBB5_2
298+
; RV64IZFINX-NEXT: # %bb.1:
299+
; RV64IZFINX-NEXT: fmin.s a0, a0, a0
300+
; RV64IZFINX-NEXT: ret
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; RV64IZFINX-NEXT: .LBB5_2:
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; RV64IZFINX-NEXT: fadd.s a1, a0, a0
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; RV64IZFINX-NEXT: fmin.s a0, a0, a1
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; RV64IZFINX-NEXT: ret
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%c = fadd nnan float %a, %a
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%1 = call float @llvm.minimum.f32(float %a, float %c)
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ret float %1
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}
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define float @fmaximum_nnan_op_f32(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmaximum_nnan_op_f32:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fadd.s fa5, fa0, fa1
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; RV32IF-NEXT: fsub.s fa4, fa0, fa1
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; RV32IF-NEXT: fmax.s fa0, fa5, fa4
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; RV32IF-NEXT: ret
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;
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; RV32IZFINX-LABEL: fmaximum_nnan_op_f32:
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; RV32IZFINX: # %bb.0:
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; RV32IZFINX-NEXT: fadd.s a2, a0, a1
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; RV32IZFINX-NEXT: fsub.s a0, a0, a1
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; RV32IZFINX-NEXT: fmax.s a0, a2, a0
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; RV32IZFINX-NEXT: ret
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;
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; RV64IF-LABEL: fmaximum_nnan_op_f32:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fadd.s fa5, fa0, fa1
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; RV64IF-NEXT: fsub.s fa4, fa0, fa1
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; RV64IF-NEXT: fmax.s fa0, fa5, fa4
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; RV64IF-NEXT: ret
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;
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; RV64IZFINX-LABEL: fmaximum_nnan_op_f32:
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; RV64IZFINX: # %bb.0:
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; RV64IZFINX-NEXT: fadd.s a2, a0, a1
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; RV64IZFINX-NEXT: fsub.s a0, a0, a1
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; RV64IZFINX-NEXT: fmax.s a0, a2, a0
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; RV64IZFINX-NEXT: ret
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%c = fadd nnan float %a, %b
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%d = fsub nnan float %a, %b
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%1 = call float @llvm.maximum.f32(float %c, float %d)
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ret float %1
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}

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