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[RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change
Rename vfredsum and vfwredsum to vfredusum and vfwredusum. Add aliases for vfredsum and vfwredsum. Reviewed By: luismarques, HsiangKai, khchen, frasercrmck, kito-cheng, craig.topper Differential Revision: https://reviews.llvm.org/D105690
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19 files changed

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lines changed

‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2006,11 +2006,11 @@ let HasMaskedOffOperand = false in {
20062006
// 15.3. Vector Single-Width Floating-Point Reduction Instructions
20072007
defm vfredmax : RVVFloatingReductionBuiltin;
20082008
defm vfredmin : RVVFloatingReductionBuiltin;
2009-
defm vfredsum : RVVFloatingReductionBuiltin;
2009+
defm vfredusum : RVVFloatingReductionBuiltin;
20102010
defm vfredosum : RVVFloatingReductionBuiltin;
20112011

20122012
// 15.4. Vector Widening Floating-Point Reduction Instructions
2013-
defm vfwredsum : RVVFloatingWidenReductionBuiltin;
2013+
defm vfwredusum : RVVFloatingWidenReductionBuiltin;
20142014
defm vfwredosum : RVVFloatingWidenReductionBuiltin;
20152015
}
20162016

‎clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c

Lines changed: 118 additions & 100 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c

Lines changed: 70 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -5,114 +5,124 @@
55

66
#include <riscv_vector.h>
77

8-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1(
8+
//
9+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1(
910
// CHECK-RV64-NEXT: entry:
10-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
11+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
1112
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1213
//
13-
vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1(vfloat64m1_t dst,
14-
vfloat32mf2_t vector,
15-
vfloat64m1_t scalar, size_t vl) {
16-
return vfwredsum(dst, vector, scalar, vl);
14+
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat64m1_t dst,
15+
vfloat32mf2_t vector,
16+
vfloat64m1_t scalar, size_t vl) {
17+
return vfwredusum(dst, vector, scalar, vl);
1718
}
1819

19-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1(
20+
//
21+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1(
2022
// CHECK-RV64-NEXT: entry:
21-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
23+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
2224
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
2325
//
24-
vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1(vfloat64m1_t dst,
25-
vfloat32m1_t vector,
26-
vfloat64m1_t scalar, size_t vl) {
27-
return vfwredsum(dst, vector, scalar, vl);
26+
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat64m1_t dst,
27+
vfloat32m1_t vector,
28+
vfloat64m1_t scalar, size_t vl) {
29+
return vfwredusum(dst, vector, scalar, vl);
2830
}
2931

30-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1(
32+
//
33+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1(
3134
// CHECK-RV64-NEXT: entry:
32-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
35+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
3336
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
3437
//
35-
vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1(vfloat64m1_t dst,
36-
vfloat32m2_t vector,
37-
vfloat64m1_t scalar, size_t vl) {
38-
return vfwredsum(dst, vector, scalar, vl);
38+
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat64m1_t dst,
39+
vfloat32m2_t vector,
40+
vfloat64m1_t scalar, size_t vl) {
41+
return vfwredusum(dst, vector, scalar, vl);
3942
}
4043

41-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1(
44+
//
45+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1(
4246
// CHECK-RV64-NEXT: entry:
43-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
47+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
4448
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
4549
//
46-
vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1(vfloat64m1_t dst,
47-
vfloat32m4_t vector,
48-
vfloat64m1_t scalar, size_t vl) {
49-
return vfwredsum(dst, vector, scalar, vl);
50+
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat64m1_t dst,
51+
vfloat32m4_t vector,
52+
vfloat64m1_t scalar, size_t vl) {
53+
return vfwredusum(dst, vector, scalar, vl);
5054
}
5155

52-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1(
56+
//
57+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1(
5358
// CHECK-RV64-NEXT: entry:
54-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
59+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
5560
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
5661
//
57-
vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1(vfloat64m1_t dst,
58-
vfloat32m8_t vector,
59-
vfloat64m1_t scalar, size_t vl) {
60-
return vfwredsum(dst, vector, scalar, vl);
62+
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat64m1_t dst,
63+
vfloat32m8_t vector,
64+
vfloat64m1_t scalar, size_t vl) {
65+
return vfwredusum(dst, vector, scalar, vl);
6166
}
6267

63-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32mf2_f64m1_m(
68+
//
69+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_m(
6470
// CHECK-RV64-NEXT: entry:
65-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
71+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
6672
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
6773
//
68-
vfloat64m1_t test_vfwredsum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
69-
vfloat32mf2_t vector,
70-
vfloat64m1_t scalar, size_t vl) {
71-
return vfwredsum(mask, dst, vector, scalar, vl);
74+
vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
75+
vfloat32mf2_t vector,
76+
vfloat64m1_t scalar, size_t vl) {
77+
return vfwredusum(mask, dst, vector, scalar, vl);
7278
}
7379

74-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m1_f64m1_m(
80+
//
81+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1_m(
7582
// CHECK-RV64-NEXT: entry:
76-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
83+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
7784
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
7885
//
79-
vfloat64m1_t test_vfwredsum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst,
80-
vfloat32m1_t vector,
81-
vfloat64m1_t scalar, size_t vl) {
82-
return vfwredsum(mask, dst, vector, scalar, vl);
86+
vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst,
87+
vfloat32m1_t vector,
88+
vfloat64m1_t scalar, size_t vl) {
89+
return vfwredusum(mask, dst, vector, scalar, vl);
8390
}
8491

85-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m2_f64m1_m(
92+
//
93+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1_m(
8694
// CHECK-RV64-NEXT: entry:
87-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
95+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
8896
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
8997
//
90-
vfloat64m1_t test_vfwredsum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst,
91-
vfloat32m2_t vector,
92-
vfloat64m1_t scalar, size_t vl) {
93-
return vfwredsum(mask, dst, vector, scalar, vl);
98+
vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst,
99+
vfloat32m2_t vector,
100+
vfloat64m1_t scalar, size_t vl) {
101+
return vfwredusum(mask, dst, vector, scalar, vl);
94102
}
95103

96-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m4_f64m1_m(
104+
//
105+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1_m(
97106
// CHECK-RV64-NEXT: entry:
98-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
107+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
99108
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
100109
//
101-
vfloat64m1_t test_vfwredsum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
102-
vfloat32m4_t vector,
103-
vfloat64m1_t scalar, size_t vl) {
104-
return vfwredsum(mask, dst, vector, scalar, vl);
110+
vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
111+
vfloat32m4_t vector,
112+
vfloat64m1_t scalar, size_t vl) {
113+
return vfwredusum(mask, dst, vector, scalar, vl);
105114
}
106115

107-
// CHECK-RV64-LABEL: @test_vfwredsum_vs_f32m8_f64m1_m(
116+
//
117+
// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1_m(
108118
// CHECK-RV64-NEXT: entry:
109-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
119+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
110120
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
111121
//
112-
vfloat64m1_t test_vfwredsum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst,
113-
vfloat32m8_t vector,
114-
vfloat64m1_t scalar, size_t vl) {
115-
return vfwredsum(mask, dst, vector, scalar, vl);
122+
vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst,
123+
vfloat32m8_t vector,
124+
vfloat64m1_t scalar, size_t vl) {
125+
return vfwredusum(mask, dst, vector, scalar, vl);
116126
}
117127

118128
// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1(

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