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Merge commit 'e47ab56398c3' from llvm.org/main into next
2 parents d4f8fd0 + e47ab56 commit 063ceeb

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‎llvm/test/CodeGen/RISCV/rv32zba.ll

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -785,3 +785,84 @@ define i32 @add8208(i32 %a) {
785785
%c = add i32 %a, 8208
786786
ret i32 %c
787787
}
788+
789+
define i32 @addshl_5_6(i32 %a, i32 %b) {
790+
; RV32I-LABEL: addshl_5_6:
791+
; RV32I: # %bb.0:
792+
; RV32I-NEXT: slli a0, a0, 5
793+
; RV32I-NEXT: slli a1, a1, 6
794+
; RV32I-NEXT: add a0, a0, a1
795+
; RV32I-NEXT: ret
796+
;
797+
; RV32B-LABEL: addshl_5_6:
798+
; RV32B: # %bb.0:
799+
; RV32B-NEXT: slli a0, a0, 5
800+
; RV32B-NEXT: slli a1, a1, 6
801+
; RV32B-NEXT: add a0, a0, a1
802+
; RV32B-NEXT: ret
803+
;
804+
; RV32ZBA-LABEL: addshl_5_6:
805+
; RV32ZBA: # %bb.0:
806+
; RV32ZBA-NEXT: slli a0, a0, 5
807+
; RV32ZBA-NEXT: slli a1, a1, 6
808+
; RV32ZBA-NEXT: add a0, a0, a1
809+
; RV32ZBA-NEXT: ret
810+
%c = shl i32 %a, 5
811+
%d = shl i32 %b, 6
812+
%e = add i32 %c, %d
813+
ret i32 %e
814+
}
815+
816+
define i32 @addshl_5_7(i32 %a, i32 %b) {
817+
; RV32I-LABEL: addshl_5_7:
818+
; RV32I: # %bb.0:
819+
; RV32I-NEXT: slli a0, a0, 5
820+
; RV32I-NEXT: slli a1, a1, 7
821+
; RV32I-NEXT: add a0, a0, a1
822+
; RV32I-NEXT: ret
823+
;
824+
; RV32B-LABEL: addshl_5_7:
825+
; RV32B: # %bb.0:
826+
; RV32B-NEXT: slli a0, a0, 5
827+
; RV32B-NEXT: slli a1, a1, 7
828+
; RV32B-NEXT: add a0, a0, a1
829+
; RV32B-NEXT: ret
830+
;
831+
; RV32ZBA-LABEL: addshl_5_7:
832+
; RV32ZBA: # %bb.0:
833+
; RV32ZBA-NEXT: slli a0, a0, 5
834+
; RV32ZBA-NEXT: slli a1, a1, 7
835+
; RV32ZBA-NEXT: add a0, a0, a1
836+
; RV32ZBA-NEXT: ret
837+
%c = shl i32 %a, 5
838+
%d = shl i32 %b, 7
839+
%e = add i32 %c, %d
840+
ret i32 %e
841+
}
842+
843+
define i32 @addshl_5_8(i32 %a, i32 %b) {
844+
; RV32I-LABEL: addshl_5_8:
845+
; RV32I: # %bb.0:
846+
; RV32I-NEXT: slli a0, a0, 5
847+
; RV32I-NEXT: slli a1, a1, 8
848+
; RV32I-NEXT: add a0, a0, a1
849+
; RV32I-NEXT: ret
850+
;
851+
; RV32B-LABEL: addshl_5_8:
852+
; RV32B: # %bb.0:
853+
; RV32B-NEXT: slli a0, a0, 5
854+
; RV32B-NEXT: slli a1, a1, 8
855+
; RV32B-NEXT: add a0, a0, a1
856+
; RV32B-NEXT: ret
857+
;
858+
; RV32ZBA-LABEL: addshl_5_8:
859+
; RV32ZBA: # %bb.0:
860+
; RV32ZBA-NEXT: slli a0, a0, 5
861+
; RV32ZBA-NEXT: slli a1, a1, 8
862+
; RV32ZBA-NEXT: add a0, a0, a1
863+
; RV32ZBA-NEXT: ret
864+
%c = shl i32 %a, 5
865+
%d = shl i32 %b, 8
866+
%e = add i32 %c, %d
867+
ret i32 %e
868+
}

‎llvm/test/CodeGen/RISCV/rv64zba.ll

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1399,3 +1399,165 @@ define i64 @add8208(i64 %a) {
13991399
%c = add i64 %a, 8208
14001400
ret i64 %c
14011401
}
1402+
1403+
define signext i32 @addshl32_5_6(i32 signext %a, i32 signext %b) {
1404+
; RV64I-LABEL: addshl32_5_6:
1405+
; RV64I: # %bb.0:
1406+
; RV64I-NEXT: slliw a0, a0, 5
1407+
; RV64I-NEXT: slliw a1, a1, 6
1408+
; RV64I-NEXT: addw a0, a0, a1
1409+
; RV64I-NEXT: ret
1410+
;
1411+
; RV64B-LABEL: addshl32_5_6:
1412+
; RV64B: # %bb.0:
1413+
; RV64B-NEXT: slliw a0, a0, 5
1414+
; RV64B-NEXT: slliw a1, a1, 6
1415+
; RV64B-NEXT: addw a0, a0, a1
1416+
; RV64B-NEXT: ret
1417+
;
1418+
; RV64ZBA-LABEL: addshl32_5_6:
1419+
; RV64ZBA: # %bb.0:
1420+
; RV64ZBA-NEXT: slliw a0, a0, 5
1421+
; RV64ZBA-NEXT: slliw a1, a1, 6
1422+
; RV64ZBA-NEXT: addw a0, a0, a1
1423+
; RV64ZBA-NEXT: ret
1424+
%c = shl i32 %a, 5
1425+
%d = shl i32 %b, 6
1426+
%e = add i32 %c, %d
1427+
ret i32 %e
1428+
}
1429+
1430+
define i64 @addshl64_5_6(i64 %a, i64 %b) {
1431+
; RV64I-LABEL: addshl64_5_6:
1432+
; RV64I: # %bb.0:
1433+
; RV64I-NEXT: slli a0, a0, 5
1434+
; RV64I-NEXT: slli a1, a1, 6
1435+
; RV64I-NEXT: add a0, a0, a1
1436+
; RV64I-NEXT: ret
1437+
;
1438+
; RV64B-LABEL: addshl64_5_6:
1439+
; RV64B: # %bb.0:
1440+
; RV64B-NEXT: slli a0, a0, 5
1441+
; RV64B-NEXT: slli a1, a1, 6
1442+
; RV64B-NEXT: add a0, a0, a1
1443+
; RV64B-NEXT: ret
1444+
;
1445+
; RV64ZBA-LABEL: addshl64_5_6:
1446+
; RV64ZBA: # %bb.0:
1447+
; RV64ZBA-NEXT: slli a0, a0, 5
1448+
; RV64ZBA-NEXT: slli a1, a1, 6
1449+
; RV64ZBA-NEXT: add a0, a0, a1
1450+
; RV64ZBA-NEXT: ret
1451+
%c = shl i64 %a, 5
1452+
%d = shl i64 %b, 6
1453+
%e = add i64 %c, %d
1454+
ret i64 %e
1455+
}
1456+
1457+
define signext i32 @addshl32_5_7(i32 signext %a, i32 signext %b) {
1458+
; RV64I-LABEL: addshl32_5_7:
1459+
; RV64I: # %bb.0:
1460+
; RV64I-NEXT: slliw a0, a0, 5
1461+
; RV64I-NEXT: slliw a1, a1, 7
1462+
; RV64I-NEXT: addw a0, a0, a1
1463+
; RV64I-NEXT: ret
1464+
;
1465+
; RV64B-LABEL: addshl32_5_7:
1466+
; RV64B: # %bb.0:
1467+
; RV64B-NEXT: slliw a0, a0, 5
1468+
; RV64B-NEXT: slliw a1, a1, 7
1469+
; RV64B-NEXT: addw a0, a0, a1
1470+
; RV64B-NEXT: ret
1471+
;
1472+
; RV64ZBA-LABEL: addshl32_5_7:
1473+
; RV64ZBA: # %bb.0:
1474+
; RV64ZBA-NEXT: slliw a0, a0, 5
1475+
; RV64ZBA-NEXT: slliw a1, a1, 7
1476+
; RV64ZBA-NEXT: addw a0, a0, a1
1477+
; RV64ZBA-NEXT: ret
1478+
%c = shl i32 %a, 5
1479+
%d = shl i32 %b, 7
1480+
%e = add i32 %c, %d
1481+
ret i32 %e
1482+
}
1483+
1484+
define i64 @addshl64_5_7(i64 %a, i64 %b) {
1485+
; RV64I-LABEL: addshl64_5_7:
1486+
; RV64I: # %bb.0:
1487+
; RV64I-NEXT: slli a0, a0, 5
1488+
; RV64I-NEXT: slli a1, a1, 7
1489+
; RV64I-NEXT: add a0, a0, a1
1490+
; RV64I-NEXT: ret
1491+
;
1492+
; RV64B-LABEL: addshl64_5_7:
1493+
; RV64B: # %bb.0:
1494+
; RV64B-NEXT: slli a0, a0, 5
1495+
; RV64B-NEXT: slli a1, a1, 7
1496+
; RV64B-NEXT: add a0, a0, a1
1497+
; RV64B-NEXT: ret
1498+
;
1499+
; RV64ZBA-LABEL: addshl64_5_7:
1500+
; RV64ZBA: # %bb.0:
1501+
; RV64ZBA-NEXT: slli a0, a0, 5
1502+
; RV64ZBA-NEXT: slli a1, a1, 7
1503+
; RV64ZBA-NEXT: add a0, a0, a1
1504+
; RV64ZBA-NEXT: ret
1505+
%c = shl i64 %a, 5
1506+
%d = shl i64 %b, 7
1507+
%e = add i64 %c, %d
1508+
ret i64 %e
1509+
}
1510+
1511+
define signext i32 @addshl32_5_8(i32 signext %a, i32 signext %b) {
1512+
; RV64I-LABEL: addshl32_5_8:
1513+
; RV64I: # %bb.0:
1514+
; RV64I-NEXT: slliw a0, a0, 5
1515+
; RV64I-NEXT: slliw a1, a1, 8
1516+
; RV64I-NEXT: addw a0, a0, a1
1517+
; RV64I-NEXT: ret
1518+
;
1519+
; RV64B-LABEL: addshl32_5_8:
1520+
; RV64B: # %bb.0:
1521+
; RV64B-NEXT: slliw a0, a0, 5
1522+
; RV64B-NEXT: slliw a1, a1, 8
1523+
; RV64B-NEXT: addw a0, a0, a1
1524+
; RV64B-NEXT: ret
1525+
;
1526+
; RV64ZBA-LABEL: addshl32_5_8:
1527+
; RV64ZBA: # %bb.0:
1528+
; RV64ZBA-NEXT: slliw a0, a0, 5
1529+
; RV64ZBA-NEXT: slliw a1, a1, 8
1530+
; RV64ZBA-NEXT: addw a0, a0, a1
1531+
; RV64ZBA-NEXT: ret
1532+
%c = shl i32 %a, 5
1533+
%d = shl i32 %b, 8
1534+
%e = add i32 %c, %d
1535+
ret i32 %e
1536+
}
1537+
1538+
define i64 @addshl64_5_8(i64 %a, i64 %b) {
1539+
; RV64I-LABEL: addshl64_5_8:
1540+
; RV64I: # %bb.0:
1541+
; RV64I-NEXT: slli a0, a0, 5
1542+
; RV64I-NEXT: slli a1, a1, 8
1543+
; RV64I-NEXT: add a0, a0, a1
1544+
; RV64I-NEXT: ret
1545+
;
1546+
; RV64B-LABEL: addshl64_5_8:
1547+
; RV64B: # %bb.0:
1548+
; RV64B-NEXT: slli a0, a0, 5
1549+
; RV64B-NEXT: slli a1, a1, 8
1550+
; RV64B-NEXT: add a0, a0, a1
1551+
; RV64B-NEXT: ret
1552+
;
1553+
; RV64ZBA-LABEL: addshl64_5_8:
1554+
; RV64ZBA: # %bb.0:
1555+
; RV64ZBA-NEXT: slli a0, a0, 5
1556+
; RV64ZBA-NEXT: slli a1, a1, 8
1557+
; RV64ZBA-NEXT: add a0, a0, a1
1558+
; RV64ZBA-NEXT: ret
1559+
%c = shl i64 %a, 5
1560+
%d = shl i64 %b, 8
1561+
%e = add i64 %c, %d
1562+
ret i64 %e
1563+
}

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