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[ARM][LowOverheadLoops] Skip debug values
While iterating through the loop, don't inspect any dbg values. Differential Revision: https://reviews.llvm.org/D73688
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‎llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -694,7 +694,9 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
694694
// whether we can convert that predicate using tail predication.
695695
for (auto *MBB : reverse(ML->getBlocks())) {
696696
for (auto &MI : *MBB) {
697-
if (MI.getOpcode() == ARM::t2LoopDec)
697+
if (MI.isDebugValue())
698+
continue;
699+
else if (MI.getOpcode() == ARM::t2LoopDec)
698700
LoLoop.Dec = &MI;
699701
else if (MI.getOpcode() == ARM::t2LoopEnd)
700702
LoLoop.End = &MI;

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir

Lines changed: 297 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,297 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
3+
--- |
4+
define dso_local arm_aapcs_vfpcc void @skip_debug(i32* nocapture %a, i16* nocapture readonly %b, i32 %N) !dbg !8 {
5+
entry:
6+
call void @llvm.dbg.value(metadata i32* %a, metadata !17, metadata !DIExpression()), !dbg !23
7+
call void @llvm.dbg.value(metadata i16* %b, metadata !18, metadata !DIExpression()), !dbg !23
8+
call void @llvm.dbg.value(metadata i32 %N, metadata !19, metadata !DIExpression()), !dbg !23
9+
%0 = load i32, i32* %a, align 4, !dbg !24
10+
call void @llvm.dbg.value(metadata i32 %0, metadata !20, metadata !DIExpression()), !dbg !23
11+
call void @llvm.dbg.value(metadata i32 0, metadata !21, metadata !DIExpression()), !dbg !29
12+
%cmp7 = icmp eq i32 %N, 0, !dbg !30
13+
%1 = add i32 %N, 3, !dbg !32
14+
%2 = lshr i32 %1, 2, !dbg !32
15+
%3 = shl nuw i32 %2, 2, !dbg !32
16+
%4 = add i32 %3, -4, !dbg !32
17+
%5 = lshr i32 %4, 2, !dbg !32
18+
%6 = add nuw nsw i32 %5, 1, !dbg !32
19+
br i1 %cmp7, label %for.cond.cleanup, label %vector.ph, !dbg !32
20+
21+
vector.ph: ; preds = %entry
22+
%7 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %0, i32 0, !dbg !32
23+
call void @llvm.set.loop.iterations.i32(i32 %6), !dbg !32
24+
%8 = shl i32 %5, 2, !dbg !32
25+
%9 = sub i32 %N, %8, !dbg !32
26+
br label %vector.body, !dbg !32
27+
28+
vector.body: ; preds = %vector.body, %vector.ph
29+
%lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %b, %vector.ph ], !dbg !33
30+
%vec.phi = phi <4 x i32> [ %7, %vector.ph ], [ %15, %vector.body ]
31+
%10 = phi i32 [ %6, %vector.ph ], [ %16, %vector.body ]
32+
%11 = phi i32 [ %N, %vector.ph ], [ %13, %vector.body ]
33+
%lsr.iv14 = bitcast i16* %lsr.iv to <4 x i16>*
34+
%12 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %11), !dbg !34
35+
%13 = sub i32 %11, 4, !dbg !34
36+
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv14, i32 2, <4 x i1> %12, <4 x i16> undef), !dbg !34
37+
%14 = sext <4 x i16> %wide.masked.load to <4 x i32>, !dbg !34
38+
%15 = sub <4 x i32> %vec.phi, %14, !dbg !38
39+
%scevgep = getelementptr i16, i16* %lsr.iv, i32 4, !dbg !33
40+
%16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %10, i32 1), !dbg !33
41+
%17 = icmp ne i32 %16, 0, !dbg !33
42+
br i1 %17, label %vector.body, label %middle.block, !dbg !33
43+
44+
middle.block: ; preds = %vector.body
45+
%vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ]
46+
%.lcssa = phi <4 x i32> [ %15, %vector.body ], !dbg !38
47+
%18 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %9), !dbg !34
48+
%19 = select <4 x i1> %18, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa, !dbg !38
49+
%20 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %19), !dbg !32
50+
br label %for.cond.cleanup, !dbg !42
51+
52+
for.cond.cleanup: ; preds = %middle.block, %entry
53+
%temp.0.lcssa = phi i32 [ %0, %entry ], [ %20, %middle.block ], !dbg !23
54+
call void @llvm.dbg.value(metadata i32 %temp.0.lcssa, metadata !20, metadata !DIExpression()), !dbg !23
55+
store i32 %temp.0.lcssa, i32* %a, align 4, !dbg !42
56+
ret void, !dbg !43
57+
}
58+
59+
declare void @llvm.dbg.value(metadata, metadata, metadata)
60+
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
61+
declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
62+
declare void @llvm.set.loop.iterations.i32(i32)
63+
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
64+
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
65+
66+
!llvm.dbg.cu = !{!0}
67+
!llvm.module.flags = !{!3, !4, !5, !6}
68+
!llvm.ident = !{!7}
69+
70+
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
71+
!1 = !DIFile(filename: "skip-debug", directory: "")
72+
!2 = !{}
73+
!3 = !{i32 7, !"Dwarf Version", i32 4}
74+
!4 = !{i32 2, !"Debug Info Version", i32 3}
75+
!5 = !{i32 1, !"wchar_size", i32 4}
76+
!6 = !{i32 1, !"min_enum_size", i32 4}
77+
!7 = !{!""}
78+
!8 = distinct !DISubprogram(name: "skip_debug", scope: !1, file: !1, line: 2, type: !9, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)
79+
!9 = !DISubroutineType(types: !10)
80+
!10 = !{null, !11, !13, !15}
81+
!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32)
82+
!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
83+
!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 32)
84+
!14 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)
85+
!15 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
86+
!16 = !{!17, !18, !19, !20, !21}
87+
!17 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 2, type: !11)
88+
!18 = !DILocalVariable(name: "b", arg: 2, scope: !8, file: !1, line: 2, type: !13)
89+
!19 = !DILocalVariable(name: "N", arg: 3, scope: !8, file: !1, line: 2, type: !15)
90+
!20 = !DILocalVariable(name: "temp", scope: !8, file: !1, line: 3, type: !12)
91+
!21 = !DILocalVariable(name: "i", scope: !22, file: !1, line: 4, type: !15)
92+
!22 = distinct !DILexicalBlock(scope: !8, file: !1, line: 4, column: 3)
93+
!23 = !DILocation(line: 0, scope: !8)
94+
!24 = !DILocation(line: 3, column: 14, scope: !8)
95+
!25 = !{!26, !26, i64 0}
96+
!26 = !{!"int", !27, i64 0}
97+
!27 = !{!"omnipotent char", !28, i64 0}
98+
!28 = !{!"Simple C/C++ TBAA"}
99+
!29 = !DILocation(line: 0, scope: !22)
100+
!30 = !DILocation(line: 4, column: 26, scope: !31)
101+
!31 = distinct !DILexicalBlock(scope: !22, file: !1, line: 4, column: 3)
102+
!32 = !DILocation(line: 4, column: 3, scope: !22)
103+
!33 = !DILocation(line: 4, column: 31, scope: !31)
104+
!34 = !DILocation(line: 5, column: 13, scope: !35)
105+
!35 = distinct !DILexicalBlock(scope: !31, file: !1, line: 4, column: 36)
106+
!36 = !{!37, !37, i64 0}
107+
!37 = !{!"short", !27, i64 0}
108+
!38 = !DILocation(line: 5, column: 10, scope: !35)
109+
!39 = distinct !{!39, !32, !40, !41}
110+
!40 = !DILocation(line: 6, column: 3, scope: !22)
111+
!41 = !{!"llvm.loop.isvectorized", i32 1}
112+
!42 = !DILocation(line: 7, column: 6, scope: !8)
113+
!43 = !DILocation(line: 8, column: 1, scope: !8)
114+
115+
...
116+
---
117+
name: skip_debug
118+
alignment: 2
119+
exposesReturnsTwice: false
120+
legalized: false
121+
regBankSelected: false
122+
selected: false
123+
failedISel: false
124+
tracksRegLiveness: true
125+
hasWinCFI: false
126+
registers: []
127+
liveins:
128+
- { reg: '$r0', virtual-reg: '' }
129+
- { reg: '$r1', virtual-reg: '' }
130+
- { reg: '$r2', virtual-reg: '' }
131+
frameInfo:
132+
isFrameAddressTaken: false
133+
isReturnAddressTaken: false
134+
hasStackMap: false
135+
hasPatchPoint: false
136+
stackSize: 16
137+
offsetAdjustment: -8
138+
maxAlignment: 4
139+
adjustsStack: false
140+
hasCalls: false
141+
stackProtector: ''
142+
maxCallFrameSize: 0
143+
cvBytesOfCalleeSavedRegisters: 0
144+
hasOpaqueSPAdjustment: false
145+
hasVAStart: false
146+
hasMustTailInVarArgFunc: false
147+
localFrameSize: 0
148+
savePoint: ''
149+
restorePoint: ''
150+
fixedStack: []
151+
stack:
152+
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
153+
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
154+
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
155+
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
156+
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
157+
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
158+
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
159+
stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
160+
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
161+
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
162+
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
163+
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
164+
callSites: []
165+
constants: []
166+
machineFunctionInfo: {}
167+
body: |
168+
; CHECK-LABEL: name: skip_debug
169+
; CHECK: bb.0.entry:
170+
; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
171+
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r6
172+
; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
173+
; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
174+
; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
175+
; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
176+
; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
177+
; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
178+
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
179+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
180+
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
181+
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
182+
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
183+
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
184+
; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg
185+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
186+
; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14, $noreg, debug-location !24 :: (load 4 from %ir.a)
187+
; CHECK: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25
188+
; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
189+
; CHECK: tCBZ $r2, %bb.4, debug-location !28
190+
; CHECK: bb.1.vector.ph:
191+
; CHECK: successors: %bb.2(0x80000000)
192+
; CHECK: liveins: $r0, $r1, $r2, $r12
193+
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !28
194+
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg
195+
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !28
196+
; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
197+
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !28
198+
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !28
199+
; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !28
200+
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !28
201+
; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !28
202+
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !28
203+
; CHECK: $lr = t2DLS killed renamable $lr, debug-location !28
204+
; CHECK: bb.2.vector.body:
205+
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
206+
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
207+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !30
208+
; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30
209+
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1
210+
; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30
211+
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !30 :: (load 8 from %ir.lsr.iv14, align 2)
212+
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !30
213+
; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !30
214+
; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !32
215+
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29
216+
; CHECK: bb.3.middle.block:
217+
; CHECK: successors: %bb.4(0x80000000)
218+
; CHECK: liveins: $q0, $q1, $r0, $r3
219+
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !30
220+
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !32
221+
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !28
222+
; CHECK: bb.4.for.cond.cleanup:
223+
; CHECK: liveins: $r0, $r12
224+
; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
225+
; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !33 :: (store 4 into %ir.a)
226+
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34
227+
bb.0.entry:
228+
successors: %bb.4(0x30000000), %bb.1(0x50000000)
229+
liveins: $r0, $r1, $r2, $r4, $r6, $lr
230+
231+
DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
232+
DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
233+
DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
234+
DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
235+
DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
236+
DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
237+
frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
238+
frame-setup CFI_INSTRUCTION def_cfa_offset 16
239+
frame-setup CFI_INSTRUCTION offset $lr, -4
240+
frame-setup CFI_INSTRUCTION offset $r7, -8
241+
frame-setup CFI_INSTRUCTION offset $r6, -12
242+
frame-setup CFI_INSTRUCTION offset $r4, -16
243+
$r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg
244+
frame-setup CFI_INSTRUCTION def_cfa $r7, 8
245+
renamable $r12 = t2LDRi12 renamable $r0, 0, 14, $noreg, debug-location !24 :: (load 4 from %ir.a)
246+
DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !29
247+
DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
248+
tCBZ $r2, %bb.4, debug-location !32
249+
250+
bb.1.vector.ph:
251+
successors: %bb.2(0x80000000)
252+
liveins: $r0, $r1, $r2, $r12
253+
254+
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !32
255+
renamable $lr = t2MOVi 1, 14, $noreg, $noreg
256+
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !32
257+
renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
258+
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !32
259+
renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !32
260+
renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !32
261+
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !32
262+
renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !32
263+
renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !32
264+
t2DoLoopStart renamable $lr, debug-location !32
265+
266+
bb.2.vector.body:
267+
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
268+
liveins: $lr, $q0, $r0, $r1, $r2, $r3
269+
270+
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !34
271+
DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !34
272+
$q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1
273+
MVE_VPST 8, implicit $vpr, debug-location !34
274+
renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !34 :: (load 8 from %ir.lsr.iv14, align 2)
275+
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !34
276+
renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !34
277+
renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !33
278+
renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !38
279+
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr, debug-location !33
280+
tB %bb.3, 14, $noreg, debug-location !33
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bb.3.middle.block:
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successors: %bb.4(0x80000000)
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liveins: $q0, $q1, $r0, $r3
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renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !34
287+
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !38
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renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !32
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bb.4.for.cond.cleanup:
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liveins: $r0, $r12
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DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
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t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !42 :: (store 4 into %ir.a)
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tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !43
296+
297+
...

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