Skip to content

Commit 07d68c2

Browse files
committed
[X86] Remove isel patterns that matched vXi16 X86VBroadcast with i8->i16 aextload input.
This was selecting VBROADCASTW which turned the 8-bit load into a 16-bit load if it happened to be 2 byte aligned. I have a plan to fix the regression with a follow up patch which I'll post shortly.
1 parent fc3c80c commit 07d68c2

File tree

3 files changed

+3
-17
lines changed

3 files changed

+3
-17
lines changed

llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1442,12 +1442,6 @@ let Predicates = [HasVLX, HasBWI] in {
14421442
def : Pat<(v16i16 (X86VBroadcast
14431443
(i16 (trunc (i32 (zextloadi16 addr:$src)))))),
14441444
(VPBROADCASTWZ256rm addr:$src)>;
1445-
1446-
// FIXME this is to handle aligned extloads from i8.
1447-
def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
1448-
(VPBROADCASTWZ128rm addr:$src)>;
1449-
def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
1450-
(VPBROADCASTWZ256rm addr:$src)>;
14511445
}
14521446
let Predicates = [HasBWI] in {
14531447
// loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably.
@@ -1460,10 +1454,6 @@ let Predicates = [HasBWI] in {
14601454
def : Pat<(v32i16 (X86VBroadcast
14611455
(i16 (trunc (i32 (zextloadi16 addr:$src)))))),
14621456
(VPBROADCASTWZrm addr:$src)>;
1463-
1464-
// FIXME this is to handle aligned extloads from i8.
1465-
def : Pat<(v32i16 (X86VBroadcast (loadi16 addr:$src))),
1466-
(VPBROADCASTWZrm addr:$src)>;
14671457
}
14681458

14691459
//===----------------------------------------------------------------------===//

llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7533,12 +7533,6 @@ let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
75337533
def : Pat<(v16i16 (X86VBroadcast
75347534
(i16 (trunc (i32 (zextloadi16 addr:$src)))))),
75357535
(VPBROADCASTWYrm addr:$src)>;
7536-
7537-
// FIXME this is to handle aligned extloads from i8.
7538-
def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7539-
(VPBROADCASTWrm addr:$src)>;
7540-
def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7541-
(VPBROADCASTWYrm addr:$src)>;
75427536
}
75437537

75447538
let Predicates = [HasAVX2, NoVLX] in {

llvm/test/CodeGen/X86/vector-sext.ll

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2039,7 +2039,9 @@ define <8 x i16> @load_sext_8i1_to_8i16(<8 x i1> *%ptr) {
20392039
;
20402040
; AVX2-LABEL: load_sext_8i1_to_8i16:
20412041
; AVX2: # %bb.0: # %entry
2042-
; AVX2-NEXT: vpbroadcastw (%rdi), %xmm0
2042+
; AVX2-NEXT: movzwl (%rdi), %eax
2043+
; AVX2-NEXT: vmovd %eax, %xmm0
2044+
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
20432045
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,4,8,16,32,64,128]
20442046
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
20452047
; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0

0 commit comments

Comments
 (0)