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Merge commit '983a2757b0a6' from llvm.org/main into next
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llvm/lib/Target/AArch64/AArch64CallingConvention.td

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@@ -333,7 +333,7 @@ def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[
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// The only documentation is the GHC source code, specifically the C header
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// file:
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//
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// https://github.com/ghc/ghc/blob/master/includes/stg/MachRegs.h
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// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs.h
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//
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// which defines the registers for the Spineless Tagless G-Machine (STG) that
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// GHC uses to implement lazy evaluation. The generic STG machine has a set of
@@ -344,8 +344,10 @@ def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[
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//
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// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode
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//
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// The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI
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// register mapping".
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// The AArch64 register mapping is defined in the following header file:
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//
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// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs/arm64.h
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//
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let Entry = 1 in
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def CC_AArch64_GHC : CallingConv<[

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