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[RISCV] Add Zce extension.
According to the spec, Zce is an alias for Zca, Zcb, Zcmp, and Zcmt. If F is enabled on RV32 it also includes Zcf. This patch adds the Zce and the implication rule which unfortunately requires custom handling for adding Zcf. I've also made all the Zc* extensions imply Zca. I've also added an error for Zcf without RV32. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D153742
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-23
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8 files changed

+170
-23
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‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
9494
{"zca", RISCVExtensionVersion{1, 0}},
9595
{"zcb", RISCVExtensionVersion{1, 0}},
9696
{"zcd", RISCVExtensionVersion{1, 0}},
97+
{"zce", RISCVExtensionVersion{1, 0}},
9798
{"zcf", RISCVExtensionVersion{1, 0}},
9899
{"zcmp", RISCVExtensionVersion{1, 0}},
99100
{"zcmt", RISCVExtensionVersion{1, 0}},
@@ -934,6 +935,10 @@ Error RISCVISAInfo::checkDependency() {
934935
"' extension is incompatible with '" + (HasC ? "c" : "zcd") +
935936
"' extension when 'd' extension is enabled");
936937

938+
if (XLen != 32 && Exts.count("zcf"))
939+
return createStringError(errc::invalid_argument,
940+
"'zcf' is only supported for 'rv32'");
941+
937942
// Additional dependency checks.
938943
// TODO: The 'q' extension requires rv64.
939944
// TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
@@ -948,6 +953,9 @@ static const char *ImpliedExtsXTHeadVdot[] = {"v"};
948953
static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
949954
static const char *ImpliedExtsZacas[] = {"a"};
950955
static const char *ImpliedExtsZcb[] = {"zca"};
956+
static const char *ImpliedExtsZcd[] = {"zca"};
957+
static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
958+
static const char *ImpliedExtsZcf[] = {"zca"};
951959
static const char *ImpliedExtsZcmp[] = {"zca"};
952960
static const char *ImpliedExtsZcmt[] = {"zca"};
953961
static const char *ImpliedExtsZdinx[] = {"zfinx"};
@@ -1011,6 +1019,9 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
10111019
{{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
10121020
{{"zacas"}, {ImpliedExtsZacas}},
10131021
{{"zcb"}, {ImpliedExtsZcb}},
1022+
{{"zcd"}, {ImpliedExtsZcd}},
1023+
{{"zce"}, {ImpliedExtsZce}},
1024+
{{"zcf"}, {ImpliedExtsZcf}},
10141025
{{"zcmp"}, {ImpliedExtsZcmp}},
10151026
{{"zcmt"}, {ImpliedExtsZcmt}},
10161027
{{"zdinx"}, {ImpliedExtsZdinx}},
@@ -1088,6 +1099,13 @@ void RISCVISAInfo::updateImplication() {
10881099
}
10891100
}
10901101
}
1102+
1103+
// Add Zcf if Zce and F are enabled on RV32.
1104+
if (XLen == 32 && Exts.count("zce") && Exts.count("f") &&
1105+
!Exts.count("zcf")) {
1106+
auto Version = findDefaultVersion("zcf");
1107+
addExtension("zcf", Version->Major, Version->Minor);
1108+
}
10911109
}
10921110

10931111
struct CombinedExtsEntry {

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 17 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -358,28 +358,36 @@ def FeatureStdExtZcf
358358
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
359359
[FeatureStdExtZca]>;
360360

361-
def HasStdExtCOrZcf
362-
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">,
363-
AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf),
364-
"'C' (Compressed Instructions) or "
365-
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
366-
367361
def FeatureStdExtZcmp
368362
: SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
369-
"'Zcmp' (sequenced instuctions for code-size reduction)",
363+
"'Zcmp' (sequenced instuctions for code-size reduction)",
370364
[FeatureStdExtZca]>;
371365
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
372366
AssemblerPredicate<(all_of FeatureStdExtZcmp, (not FeatureStdExtC)),
373367
"'Zcmp' (sequenced instuctions for code-size reduction)">;
374368

375369
def FeatureStdExtZcmt
376370
: SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
377-
"'Zcmt' (table jump instuctions for code-size reduction)",
378-
[FeatureStdExtZca, FeatureStdExtZicsr]>;
371+
"'Zcmt' (table jump instuctions for code-size reduction)",
372+
[FeatureStdExtZca, FeatureStdExtZicsr]>;
379373
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
380374
AssemblerPredicate<(all_of FeatureStdExtZcmt),
381375
"'Zcmt' (table jump instuctions for code-size reduction)">;
382376

377+
def FeatureStdExtZce
378+
: SubtargetFeature<"zce", "HasStdExtZce", "true",
379+
"'Zce' (Compressed extensions for microcontrollers)",
380+
[FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
381+
FeatureStdExtZcmt]>;
382+
383+
def HasStdExtCOrZcfOrZce
384+
: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
385+
"Subtarget->hasStdExtZce()">,
386+
AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
387+
FeatureStdExtZce),
388+
"'C' (Compressed Instructions) or "
389+
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
390+
383391
def FeatureNoRVCHints
384392
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
385393
"Disable RVC Hint Instructions.">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -348,7 +348,7 @@ def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
348348
}
349349

350350
let DecoderNamespace = "RISCV32Only_",
351-
Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in
351+
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
352352
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
353353
Sched<[WriteFLD32, ReadMemBase]> {
354354
bits<7> imm;
@@ -382,7 +382,7 @@ def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
382382
}
383383

384384
let DecoderNamespace = "RISCV32Only_",
385-
Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in
385+
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
386386
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
387387
Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
388388
bits<7> imm;
@@ -534,7 +534,7 @@ def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00>,
534534
}
535535

536536
let DecoderNamespace = "RISCV32Only_",
537-
Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in
537+
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
538538
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
539539
Sched<[WriteFLD32, ReadMemBase]> {
540540
let Inst{6-4} = imm{4-2};
@@ -592,7 +592,7 @@ def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00>,
592592
}
593593

594594
let DecoderNamespace = "RISCV32Only_",
595-
Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in
595+
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
596596
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
597597
Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
598598
let Inst{12-9} = imm{5-2};
@@ -743,7 +743,7 @@ def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SPMem:$rs1, 0)>;
743743
def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SPMem:$rs1, 0)>;
744744
}
745745

746-
let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
746+
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
747747
def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>;
748748
def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>;
749749
def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SPMem:$rs1, 0)>;
@@ -875,7 +875,7 @@ def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
875875
(C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
876876
} // Predicates = [HasStdExtCOrZca]
877877

878-
let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
878+
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
879879
def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
880880
(C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
881881
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
@@ -895,7 +895,7 @@ def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
895895
(C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
896896
} // Predicates = [HasStdExtCOrZca]
897897

898-
let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
898+
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
899899
def : CompressPat<(FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
900900
(C_FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
901901
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
@@ -992,7 +992,7 @@ def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
992992
(C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
993993
} // Predicates = [HasStdExtCOrZca]
994994

995-
let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
995+
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
996996
def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
997997
(C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
998998
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
@@ -1034,7 +1034,7 @@ def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
10341034
(C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
10351035
} // Predicates = [HasStdExtCOrZca]
10361036

1037-
let Predicates = [HasStdExtCOrZcf, HasStdExtF, IsRV32] in {
1037+
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
10381038
def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
10391039
(C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
10401040
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]

‎llvm/test/CodeGen/RISCV/compress-float.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,27 @@
4444
; RUN: -disable-block-placement < %t.mixedattr \
4545
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
4646
; RUN: | FileCheck -check-prefix=RV32IFDC %s
47+
;
48+
; RUN: cat %s > %t.tgtattr
49+
; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
50+
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce,+f -filetype=obj \
51+
; RUN: -disable-block-placement < %t.tgtattr \
52+
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
53+
; RUN: | FileCheck -check-prefix=RV32IFDC %s
54+
;
55+
; RUN: cat %s > %t.fnattr
56+
; RUN: echo 'attributes #0 = { nounwind "target-features"="+zce,+f" }' >> %t.fnattr
57+
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
58+
; RUN: -disable-block-placement < %t.fnattr \
59+
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
60+
; RUN: | FileCheck -check-prefix=RV32IFDC %s
61+
;
62+
; RUN: cat %s > %t.mixedattr
63+
; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
64+
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce -filetype=obj \
65+
; RUN: -disable-block-placement < %t.mixedattr \
66+
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
67+
; RUN: | FileCheck -check-prefix=RV32IFDC %s
4768

4869
; This acts as a basic correctness check for the codegen instruction compression
4970
; path, verifying that the assembled file contains compressed instructions when

‎llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -229,10 +229,10 @@
229229
# CHECK: attribute 5, "rv32i2p1_zca1p0"
230230

231231
.attribute arch, "rv32izcd1p0"
232-
# CHECK: attribute 5, "rv32i2p1_zcd1p0"
232+
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcd1p0"
233233

234234
.attribute arch, "rv32izcf1p0"
235-
# CHECK: attribute 5, "rv32i2p1_zcf1p0"
235+
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcf1p0"
236236

237237
.attribute arch, "rv32izcb1p0"
238238
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcb1p0"

‎llvm/test/MC/RISCV/option-arch.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,3 +118,9 @@ addi a0, a1, 0
118118
# Test extension name that has digits.
119119
.option arch, +zve32x
120120
# CHECK: .option arch, +zve32x
121+
122+
.option arch, rv32i
123+
.option arch, +zce, +f
124+
# CHECK-INST: flw fa0, 0(a0)
125+
# CHECK: # encoding: [0x08,0x61]
126+
c.flw fa0, 0(a0)

‎llvm/test/MC/RISCV/rv32fc-valid.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,6 @@
2121
# RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \
2222
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
2323
# RUN: | FileCheck -check-prefixes=CHECK-NO-RV32 %s
24-
# RUN: not llvm-mc -triple riscv64 -mattr=+zcf,+f \
25-
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
26-
# RUN: | FileCheck -check-prefixes=CHECK-NO-RV32 %s
2724

2825
# FIXME: error messages for rv64fc are misleading
2926

‎llvm/unittests/Support/RISCVISAInfoTest.cpp

Lines changed: 97 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -469,6 +469,11 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
469469
"'zcmt' extension is incompatible with 'zcd' extension when 'd' "
470470
"extension is enabled");
471471
}
472+
473+
for (StringRef Input : {"rv64if_zcf"}) {
474+
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
475+
"'zcf' is only supported for 'rv32'");
476+
}
472477
}
473478

474479
TEST(ToFeatureVector, IIsDroppedAndExperimentalExtensionsArePrefixed) {
@@ -507,3 +512,95 @@ TEST(OrderedExtensionMap, ExtensionsAreCorrectlyOrdered) {
507512
ElementsAre("i", "m", "l", "c", "y", "zicsr", "zmfoo", "zfinx",
508513
"zzfoo", "sbar", "sfoo", "xbar", "xfoo"));
509514
}
515+
516+
TEST(ParseArchString, ZceImplication) {
517+
auto MaybeRV32IZce = RISCVISAInfo::parseArchString("rv32izce", true);
518+
ASSERT_THAT_EXPECTED(MaybeRV32IZce, Succeeded());
519+
RISCVISAInfo::OrderedExtensionMap ExtsRV32IZce =
520+
(*MaybeRV32IZce)->getExtensions();
521+
EXPECT_EQ(ExtsRV32IZce.size(), 6UL);
522+
EXPECT_EQ(ExtsRV32IZce.count("i"), 1U);
523+
EXPECT_EQ(ExtsRV32IZce.count("zca"), 1U);
524+
EXPECT_EQ(ExtsRV32IZce.count("zcb"), 1U);
525+
EXPECT_EQ(ExtsRV32IZce.count("zce"), 1U);
526+
EXPECT_EQ(ExtsRV32IZce.count("zcmp"), 1U);
527+
EXPECT_EQ(ExtsRV32IZce.count("zcmt"), 1U);
528+
529+
auto MaybeRV32IFZce = RISCVISAInfo::parseArchString("rv32ifzce", true);
530+
ASSERT_THAT_EXPECTED(MaybeRV32IFZce, Succeeded());
531+
RISCVISAInfo::OrderedExtensionMap ExtsRV32IFZce =
532+
(*MaybeRV32IFZce)->getExtensions();
533+
EXPECT_EQ(ExtsRV32IFZce.size(), 9UL);
534+
EXPECT_EQ(ExtsRV32IFZce.count("i"), 1U);
535+
EXPECT_EQ(ExtsRV32IFZce.count("zicsr"), 1U);
536+
EXPECT_EQ(ExtsRV32IFZce.count("f"), 1U);
537+
EXPECT_EQ(ExtsRV32IFZce.count("zca"), 1U);
538+
EXPECT_EQ(ExtsRV32IFZce.count("zcb"), 1U);
539+
EXPECT_EQ(ExtsRV32IFZce.count("zce"), 1U);
540+
EXPECT_EQ(ExtsRV32IFZce.count("zcf"), 1U);
541+
EXPECT_EQ(ExtsRV32IFZce.count("zcmp"), 1U);
542+
EXPECT_EQ(ExtsRV32IFZce.count("zcmt"), 1U);
543+
544+
auto MaybeRV32IDZce = RISCVISAInfo::parseArchString("rv32idzce", true);
545+
ASSERT_THAT_EXPECTED(MaybeRV32IDZce, Succeeded());
546+
RISCVISAInfo::OrderedExtensionMap ExtsRV32IDZce =
547+
(*MaybeRV32IDZce)->getExtensions();
548+
EXPECT_EQ(ExtsRV32IDZce.size(), 10UL);
549+
EXPECT_EQ(ExtsRV32IDZce.count("i"), 1U);
550+
EXPECT_EQ(ExtsRV32IDZce.count("zicsr"), 1U);
551+
EXPECT_EQ(ExtsRV32IDZce.count("f"), 1U);
552+
EXPECT_EQ(ExtsRV32IDZce.count("d"), 1U);
553+
EXPECT_EQ(ExtsRV32IDZce.count("zca"), 1U);
554+
EXPECT_EQ(ExtsRV32IDZce.count("zcb"), 1U);
555+
EXPECT_EQ(ExtsRV32IDZce.count("zce"), 1U);
556+
EXPECT_EQ(ExtsRV32IDZce.count("zcf"), 1U);
557+
EXPECT_EQ(ExtsRV32IDZce.count("zcmp"), 1U);
558+
EXPECT_EQ(ExtsRV32IDZce.count("zcmt"), 1U);
559+
560+
auto MaybeRV64IZce = RISCVISAInfo::parseArchString("rv64izce", true);
561+
ASSERT_THAT_EXPECTED(MaybeRV64IZce, Succeeded());
562+
RISCVISAInfo::OrderedExtensionMap ExtsRV64IZce =
563+
(*MaybeRV64IZce)->getExtensions();
564+
EXPECT_EQ(ExtsRV64IZce.size(), 6UL);
565+
EXPECT_EQ(ExtsRV64IZce.count("i"), 1U);
566+
EXPECT_EQ(ExtsRV64IZce.count("zca"), 1U);
567+
EXPECT_EQ(ExtsRV64IZce.count("zcb"), 1U);
568+
EXPECT_EQ(ExtsRV64IZce.count("zce"), 1U);
569+
EXPECT_EQ(ExtsRV64IZce.count("zcmp"), 1U);
570+
EXPECT_EQ(ExtsRV64IZce.count("zcmt"), 1U);
571+
572+
auto MaybeRV64IFZce = RISCVISAInfo::parseArchString("rv64ifzce", true);
573+
ASSERT_THAT_EXPECTED(MaybeRV64IFZce, Succeeded());
574+
RISCVISAInfo::OrderedExtensionMap ExtsRV64IFZce =
575+
(*MaybeRV64IFZce)->getExtensions();
576+
EXPECT_EQ(ExtsRV64IFZce.size(), 8UL);
577+
EXPECT_EQ(ExtsRV64IFZce.count("i"), 1U);
578+
EXPECT_EQ(ExtsRV64IFZce.count("zicsr"), 1U);
579+
EXPECT_EQ(ExtsRV64IFZce.count("f"), 1U);
580+
EXPECT_EQ(ExtsRV64IFZce.count("zca"), 1U);
581+
EXPECT_EQ(ExtsRV64IFZce.count("zcb"), 1U);
582+
EXPECT_EQ(ExtsRV64IFZce.count("zce"), 1U);
583+
EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
584+
EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
585+
586+
EXPECT_EQ(ExtsRV64IFZce.count("zca"), 1U);
587+
EXPECT_EQ(ExtsRV64IFZce.count("zcb"), 1U);
588+
EXPECT_EQ(ExtsRV64IFZce.count("zce"), 1U);
589+
EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
590+
EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
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auto MaybeRV64IDZce = RISCVISAInfo::parseArchString("rv64idzce", true);
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ASSERT_THAT_EXPECTED(MaybeRV64IDZce, Succeeded());
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RISCVISAInfo::OrderedExtensionMap ExtsRV64IDZce =
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(*MaybeRV64IDZce)->getExtensions();
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EXPECT_EQ(ExtsRV64IDZce.size(), 9UL);
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EXPECT_EQ(ExtsRV64IDZce.count("i"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("zicsr"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("f"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("d"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("zca"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("zcb"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("zce"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
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EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
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}

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