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[AArch64] NFC: Regenerate aarch64-sve-asm.ll
It should use update_mir_test_checks.py instead of update_llc_test_checks.py.
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‎llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll

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1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc < %s -mtriple aarch64-none-linux-gnu -mattr=+sve -stop-after=finalize-isel | FileCheck %s --check-prefix=CHECK
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple aarch64-none-linux-gnu -mattr=+sve2p1 -stop-after=finalize-isel | FileCheck %s --check-prefix=CHECK
33

44
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
55
target triple = "aarch64-none-linux-gnu"
66

7-
; Function Attrs: nounwind readnone
8-
; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
9-
; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
10-
; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
11-
; CHECK: [[ARG4:%[0-9]+]]:zpr_3b = COPY [[ARG1]]
12-
; CHECK: INLINEASM {{.*}} [[ARG4]]
137
define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm) {
8+
; CHECK-LABEL: name: test_svadd_i8
9+
; CHECK: bb.0 (%ir-block.0):
10+
; CHECK-NEXT: liveins: $z0, $z1
11+
; CHECK-NEXT: {{ $}}
12+
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
15+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
16+
; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5046282 /* regdef:ZPR */, def %2, 5046281 /* reguse:ZPR */, [[COPY2]], 5373961 /* reguse:ZPR_3b */, [[COPY3]]
17+
; CHECK-NEXT: $z0 = COPY %2
18+
; CHECK-NEXT: RET_ReallyLR implicit $z0
1419
%1 = tail call <vscale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
1520
ret <vscale x 16 x i8> %1
1621
}
1722

18-
; Function Attrs: nounwind readnone
19-
; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
20-
; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
21-
; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
22-
; CHECK: [[ARG4:%[0-9]+]]:zpr_4b = COPY [[ARG1]]
23-
; CHECK: INLINEASM {{.*}} [[ARG4]]
2423
define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm) {
24+
; CHECK-LABEL: name: test_svsub_i64
25+
; CHECK: bb.0 (%ir-block.0):
26+
; CHECK-NEXT: liveins: $z0, $z1
27+
; CHECK-NEXT: {{ $}}
28+
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
29+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
31+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
32+
; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5046282 /* regdef:ZPR */, def %2, 5046281 /* reguse:ZPR */, [[COPY2]], 5242889 /* reguse:ZPR_4b */, [[COPY3]]
33+
; CHECK-NEXT: $z0 = COPY %2
34+
; CHECK-NEXT: RET_ReallyLR implicit $z0
2535
%1 = tail call <vscale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
2636
ret <vscale x 2 x i64> %1
2737
}
2838

29-
; Function Attrs: nounwind readnone
30-
; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
31-
; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
32-
; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
33-
; CHECK: [[ARG4:%[0-9]+]]:zpr_3b = COPY [[ARG1]]
34-
; CHECK: INLINEASM {{.*}} [[ARG4]]
3539
define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
40+
; CHECK-LABEL: name: test_svfmul_f16
41+
; CHECK: bb.0 (%ir-block.0):
42+
; CHECK-NEXT: liveins: $z0, $z1
43+
; CHECK-NEXT: {{ $}}
44+
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
45+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
46+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
47+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
48+
; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5046282 /* regdef:ZPR */, def %2, 5046281 /* reguse:ZPR */, [[COPY2]], 5373961 /* reguse:ZPR_3b */, [[COPY3]]
49+
; CHECK-NEXT: $z0 = COPY %2
50+
; CHECK-NEXT: RET_ReallyLR implicit $z0
3651
%1 = tail call <vscale x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
3752
ret <vscale x 8 x half> %1
3853
}
3954

40-
; Function Attrs: nounwind readnone
41-
; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
42-
; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
43-
; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
44-
; CHECK: [[ARG4:%[0-9]+]]:zpr_4b = COPY [[ARG1]]
45-
; CHECK: INLINEASM {{.*}} [[ARG4]]
4655
define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm) {
56+
; CHECK-LABEL: name: test_svfmul_f
57+
; CHECK: bb.0 (%ir-block.0):
58+
; CHECK-NEXT: liveins: $z0, $z1
59+
; CHECK-NEXT: {{ $}}
60+
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
61+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
62+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
63+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
64+
; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5046282 /* regdef:ZPR */, def %2, 5046281 /* reguse:ZPR */, [[COPY2]], 5242889 /* reguse:ZPR_4b */, [[COPY3]]
65+
; CHECK-NEXT: $z0 = COPY %2
66+
; CHECK-NEXT: RET_ReallyLR implicit $z0
4767
%1 = tail call <vscale x 4 x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
4868
ret <vscale x 4 x float> %1
4969
}
5070

51-
; Function Attrs: nounwind readnone
52-
; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
53-
; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
54-
; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
55-
; CHECK: [[ARG4:%[0-9]+]]:ppr_3b = COPY [[ARG3]]
56-
; CHECK: INLINEASM {{.*}} [[ARG4]]
5771
define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
72+
; CHECK-LABEL: name: test_svfadd_f16
73+
; CHECK: bb.0 (%ir-block.0):
74+
; CHECK-NEXT: liveins: $p0, $z0, $z1
75+
; CHECK-NEXT: {{ $}}
76+
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
77+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
78+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY $p0
79+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_3b = COPY [[COPY2]]
80+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
81+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
82+
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5046282 /* regdef:ZPR */, def %3, 589833 /* reguse:PPR_3b */, [[COPY3]], 5046281 /* reguse:ZPR */, [[COPY4]], 5046281 /* reguse:ZPR */, [[COPY5]]
83+
; CHECK-NEXT: $z0 = COPY %3
84+
; CHECK-NEXT: RET_ReallyLR implicit $z0
5885
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
5986
ret <vscale x 8 x half> %1
6087
}
6188

62-
; Function Attrs: nounwind readnone
63-
; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z0
64-
; CHECK: [[ARG2:%[0-9]+]]:ppr = COPY $p0
65-
; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY [[ARG2]]
66-
; CHECK: [[ARG4:%[0-9]+]]:zpr = COPY [[ARG1]]
67-
; CHECK: INLINEASM {{.*}} [[ARG3]]
6889
define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn) {
90+
; CHECK-LABEL: name: test_incp
91+
; CHECK: bb.0 (%ir-block.0):
92+
; CHECK-NEXT: liveins: $p0, $z0
93+
; CHECK-NEXT: {{ $}}
94+
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
95+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr = COPY $p0
96+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY [[COPY1]]
97+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY [[COPY]]
98+
; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5046282 /* regdef:ZPR */, def %2, 393225 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
99+
; CHECK-NEXT: $z0 = COPY %2
100+
; CHECK-NEXT: RET_ReallyLR implicit $z0
69101
%1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w,@3Upa,0"(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn)
70102
ret <vscale x 4 x i32> %1
71103
}
72104

73-
; Function Attrs: nounwind readnone
74-
; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
75-
; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
76-
; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
77-
; CHECK: [[ARG4:%[0-9]+]]:ppr_p8to15 = COPY [[ARG3]]
78-
; CHECK: INLINEASM {{.*}} [[ARG4]]
79105
define <vscale x 8 x half> @test_svfadd_f16_Uph_constraint(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
106+
; CHECK-LABEL: name: test_svfadd_f16_Uph_constraint
107+
; CHECK: bb.0 (%ir-block.0):
108+
; CHECK-NEXT: liveins: $p0, $z0, $z1
109+
; CHECK-NEXT: {{ $}}
110+
; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
111+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
112+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY $p0
113+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_p8to15 = COPY [[COPY2]]
114+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
115+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
116+
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5046282 /* regdef:ZPR */, def %3, 655369 /* reguse:PPR_p8to15 */, [[COPY3]], 5046281 /* reguse:ZPR */, [[COPY4]], 5046281 /* reguse:ZPR */, [[COPY5]]
117+
; CHECK-NEXT: $z0 = COPY %3
118+
; CHECK-NEXT: RET_ReallyLR implicit $z0
80119
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Uph,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
81120
ret <vscale x 8 x half> %1
82121
}
83-
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
84-
; CHECK: {{.*}}

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