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Tony Linthicum
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Hexagon backend support
llvm-svn: 146412
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‎llvm/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ set(LLVM_ALL_TARGETS
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CBackend
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CellSPU
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CppBackend
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Hexagon
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Mips
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MBlaze
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MSP430

‎llvm/autoconf/config.sub

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@@ -4,7 +4,7 @@
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# 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
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# 2011 Free Software Foundation, Inc.
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timestamp='2011-08-23'
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timestamp='2011-11-02'
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# This file is (in principle) common to ALL GNU software.
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# The presence of a machine in this file suggests that SOME GNU software
@@ -256,6 +256,7 @@ case $basic_machine in
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| c4x | clipper \
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| d10v | d30v | dlx | dsp16xx \
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| fido | fr30 | frv \
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| hexagon \
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| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
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| i370 | i860 | i960 | ia64 \
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| ip2k | iq2000 \
@@ -367,6 +368,7 @@ case $basic_machine in
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| elxsi-* \
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| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
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| h8300-* | h8500-* \
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| hexagon-* \
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| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
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| i*86-* | i860-* | i960-* | ia64-* \
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| ip2k-* | iq2000-* \

‎llvm/autoconf/configure.ac

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,7 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
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mips-*) llvm_cv_target_arch="Mips" ;;
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xcore-*) llvm_cv_target_arch="XCore" ;;
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msp430-*) llvm_cv_target_arch="MSP430" ;;
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hexagon-*) llvm_cv_target_arch="Hexagon" ;;
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mblaze-*) llvm_cv_target_arch="MBlaze" ;;
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ptx-*) llvm_cv_target_arch="PTX" ;;
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*) llvm_cv_target_arch="Unknown" ;;
@@ -503,6 +504,7 @@ else
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Mips) AC_SUBST(TARGET_HAS_JIT,1) ;;
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XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
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MSP430) AC_SUBST(TARGET_HAS_JIT,0) ;;
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Hexagon) AC_SUBST(TARGET_HAS_JIT,0) ;;
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MBlaze) AC_SUBST(TARGET_HAS_JIT,0) ;;
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PTX) AC_SUBST(TARGET_HAS_JIT,0) ;;
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*) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -615,14 +617,14 @@ dnl Allow specific targets to be specified for building (or not)
615617
TARGETS_TO_BUILD=""
616618
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
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[Build specific host targets: all or target1,target2,... Valid targets are:
618-
host, x86, x86_64, sparc, powerpc, arm, mips, spu,
620+
host, x86, x86_64, sparc, powerpc, arm, mips, spu, hexagon,
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xcore, msp430, ptx, cbe, and cpp (default=all)]),,
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enableval=all)
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if test "$enableval" = host-only ; then
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enableval=host
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fi
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case "$enableval" in
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all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
627+
all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX Hexagon" ;;
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*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
627629
case "$a_target" in
628630
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -636,6 +638,7 @@ case "$enableval" in
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msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
637639
cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
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cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
641+
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
639642
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
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ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
641644
host) case "$llvm_cv_target_arch" in
@@ -649,6 +652,7 @@ case "$enableval" in
649652
CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
650653
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
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MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
655+
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
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PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
653657
*) AC_MSG_ERROR([Can not set target to build]) ;;
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esac ;;

‎llvm/configure

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Original file line numberDiff line numberDiff line change
@@ -1419,7 +1419,7 @@ Optional Features:
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--enable-targets Build specific host targets: all or
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target1,target2,... Valid targets are: host, x86,
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x86_64, sparc, powerpc, arm, mips, spu, xcore,
1422-
msp430, ptx, cbe, and cpp (default=all)
1422+
hexagon, msp430, ptx, cbe, and cpp (default=all)
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--enable-cbe-printf-a Enable C Backend output with hex floating point via
14241424
%a (default is YES)
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--enable-bindings Build specific language bindings:
@@ -3883,6 +3883,7 @@ else
38833883
mips-*) llvm_cv_target_arch="Mips" ;;
38843884
xcore-*) llvm_cv_target_arch="XCore" ;;
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msp430-*) llvm_cv_target_arch="MSP430" ;;
3886+
hexagon-*) llvm_cv_target_arch="Hexagon" ;;
38863887
mblaze-*) llvm_cv_target_arch="MBlaze" ;;
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ptx-*) llvm_cv_target_arch="PTX" ;;
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*) llvm_cv_target_arch="Unknown" ;;
@@ -5102,6 +5103,8 @@ else
51025103
XCore) TARGET_HAS_JIT=0
51035104
;;
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MSP430) TARGET_HAS_JIT=0
5106+
;;
5107+
Hexagon) TARGET_HAS_JIT=0
51055108
;;
51065109
MBlaze) TARGET_HAS_JIT=0
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;;
@@ -5291,7 +5294,7 @@ if test "$enableval" = host-only ; then
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enableval=host
52925295
fi
52935296
case "$enableval" in
5294-
all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
5297+
all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX Hexagon" ;;
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*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
52965299
case "$a_target" in
52975300
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5305,6 +5308,7 @@ case "$enableval" in
53055308
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
53065309
cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;;
53075310
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
5311+
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
53085312
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
53095313
ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
53105314
host) case "$llvm_cv_target_arch" in
@@ -5318,6 +5322,7 @@ case "$enableval" in
53185322
CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
53195323
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
53205324
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
5325+
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
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PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;
53225327
*) { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
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echo "$as_me: error: Can not set target to build" >&2;}

‎llvm/docs/CodeGenerator.html

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@@ -2288,6 +2288,7 @@ <h3>
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<th>Feature</th>
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<th>ARM</th>
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<th>CellSPU</th>
2291+
<th>Hexagon</th>
22912292
<th>MBlaze</th>
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<th>MSP430</th>
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<th>Mips</th>
@@ -2302,6 +2303,7 @@ <h3>
23022303
<td><a href="#feat_reliable">is generally reliable</a></td>
23032304
<td class="yes"></td> <!-- ARM -->
23042305
<td class="no"></td> <!-- CellSPU -->
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<td class="yes"></td> <!-- Hexagon -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<td class="yes"></td> <!-- Mips -->
@@ -2316,6 +2318,7 @@ <h3>
23162318
<td><a href="#feat_asmparser">assembly parser</a></td>
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<td class="no"></td> <!-- ARM -->
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<td class="no"></td> <!-- CellSPU -->
2321+
<td class="no"></td> <!-- Hexagon -->
23192322
<td class="yes"></td> <!-- MBlaze -->
23202323
<td class="no"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
@@ -2330,6 +2333,7 @@ <h3>
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<td><a href="#feat_disassembler">disassembler</a></td>
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<td class="yes"></td> <!-- ARM -->
23322335
<td class="no"></td> <!-- CellSPU -->
2336+
<td class="no"></td> <!-- Hexagon -->
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<td class="yes"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
@@ -2344,6 +2348,7 @@ <h3>
23442348
<td><a href="#feat_inlineasm">inline asm</a></td>
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<td class="yes"></td> <!-- ARM -->
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<td class="no"></td> <!-- CellSPU -->
2351+
<td class="yes"></td> <!-- Hexagon -->
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<td class="yes"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
@@ -2358,6 +2363,7 @@ <h3>
23582363
<td><a href="#feat_jit">jit</a></td>
23592364
<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
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<td class="no"></td> <!-- CellSPU -->
2366+
<td class="no"></td> <!-- Hexagon -->
23612367
<td class="no"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
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<td class="yes"></td> <!-- Mips -->
@@ -2372,6 +2378,7 @@ <h3>
23722378
<td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
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<td class="no"></td> <!-- ARM -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- Hexagon -->
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<td class="yes"></td> <!-- MBlaze -->
23762383
<td class="no"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
@@ -2386,6 +2393,7 @@ <h3>
23862393
<td><a href="#feat_tailcall">tail calls</a></td>
23872394
<td class="yes"></td> <!-- ARM -->
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<td class="no"></td> <!-- CellSPU -->
2396+
<td class="yes"></td> <!-- Hexagon -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="unknown"></td> <!-- MSP430 -->
23912399
<td class="no"></td> <!-- Mips -->

‎llvm/include/llvm/ADT/Triple.h

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@@ -45,6 +45,7 @@ class Triple {
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4646
arm, // ARM; arm, armv.*, xscale
4747
cellspu, // CellSPU: spu, cellspu
48+
hexagon, // Hexagon: hexagon
4849
mips, // MIPS: mips, mipsallegrex
4950
mipsel, // MIPSEL: mipsel, mipsallegrexel, psp
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mips64, // MIPS64: mips64

‎llvm/include/llvm/Intrinsics.td

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@@ -444,3 +444,4 @@ include "llvm/IntrinsicsARM.td"
444444
include "llvm/IntrinsicsCellSPU.td"
445445
include "llvm/IntrinsicsXCore.td"
446446
include "llvm/IntrinsicsPTX.td"
447+
include "llvm/IntrinsicsHexagon.td"

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