Skip to content

Commit 1730b0f

Browse files
committed
[RISCV] Remove '.mask' from vcompress intrinsic name. NFC
It has a mask argument, but isn't a masked instruction. It doesn't use the mask policy of or the v0.t syntax.
1 parent a7130d8 commit 1730b0f

File tree

4 files changed

+268
-268
lines changed

4 files changed

+268
-268
lines changed

llvm/include/llvm/IR/IntrinsicsRISCV.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -740,7 +740,7 @@ let TargetPrefix = "riscv" in {
740740

741741
defm vrgather : RISCVBinaryAAX;
742742

743-
def "int_riscv_vcompress_mask" : RISCVBinaryAAAMask;
743+
def "int_riscv_vcompress" : RISCVBinaryAAAMask;
744744

745745
defm vaaddu : RISCVSaturatingBinaryAAX;
746746
defm vaadd : RISCVSaturatingBinaryAAX;

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -947,7 +947,7 @@ multiclass VPseudoUnaryV_M {
947947
multiclass VPseudoUnaryV_V_AnyMask {
948948
foreach m = MxList.m in {
949949
let VLMul = m.value in
950-
def _VM # "_" # m.MX # "_MASK" : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>;
950+
def _VM # "_" # m.MX : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>;
951951
}
952952
}
953953

@@ -1404,12 +1404,12 @@ class VPatUnaryAnyMask<string intrinsic,
14041404
LMULInfo vlmul,
14051405
VReg result_reg_class,
14061406
VReg op1_reg_class> :
1407-
Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
1407+
Pat<(result_type (!cast<Intrinsic>(intrinsic)
14081408
(result_type result_reg_class:$merge),
14091409
(op1_type op1_reg_class:$rs1),
14101410
(mask_type VR:$rs2),
14111411
(XLenVT GPR:$vl))),
1412-
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
1412+
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
14131413
(result_type result_reg_class:$merge),
14141414
(op1_type op1_reg_class:$rs1),
14151415
(mask_type VR:$rs2),

0 commit comments

Comments
 (0)