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Merge commit '6a85cf8fc043' from llvm.org/main into next
2 parents 63a64d4 + 6a85cf8 commit 1779857

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llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

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@@ -6032,6 +6032,17 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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if (N1.getValueType().getScalarType() == MVT::i1)
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return getNode(ISD::VECREDUCE_AND, DL, VT, N1);
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break;
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case ISD::SPLAT_VECTOR:
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assert(VT.isVector() && "Wrong return type!");
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// FIXME: Hexagon uses i32 scalar for a floating point zero vector so allow
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// that for now.
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assert((VT.getVectorElementType() == N1.getValueType() ||
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(VT.isFloatingPoint() && N1.getValueType() == MVT::i32) ||
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(VT.getVectorElementType().isInteger() &&
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N1.getValueType().isInteger() &&
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VT.getVectorElementType().bitsLE(N1.getValueType()))) &&
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"Wrong operand type!");
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break;
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}
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SDNode *N;

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