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[FMV] Use lexicographic order of feature names when mangling. (llvm#83464)
This decouples feature priorities from name mangling. Doing so will prevent ABI breakages in case we change the feature priorities. Formalized in ACLE here: ARM-software/acle#303. Cherry-pick: e81ef46
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5 files changed

+96
-55
lines changed

5 files changed

+96
-55
lines changed

‎clang/lib/CodeGen/Targets/AArch64.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -838,13 +838,9 @@ void AArch64ABIInfo::appendAttributeMangling(StringRef AttrStr,
838838
for (auto &Feat : Features)
839839
Feat = Feat.trim();
840840

841-
// FIXME: It was brought up in #79316 that sorting the features which are
842-
// used for mangling based on their multiversion priority is not a good
843-
// practice. Changing the feature priorities will break the ABI. Perhaps
844-
// it would be preferable to perform a lexicographical sort instead.
845841
const TargetInfo &TI = CGT.getTarget();
846842
llvm::sort(Features, [&TI](const StringRef LHS, const StringRef RHS) {
847-
return TI.multiVersionSortPriority(LHS) < TI.multiVersionSortPriority(RHS);
843+
return LHS.compare(RHS) < 0;
848844
});
849845

850846
for (auto &Feat : Features)

‎clang/test/CodeGen/attr-target-clones-aarch64.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
4343
// CHECK: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
4444
//.
4545
// CHECK: Function Attrs: noinline nounwind optnone
46-
// CHECK-LABEL: @ftc._MlseMaes(
46+
// CHECK-LABEL: @ftc._MaesMlse(
4747
// CHECK-NEXT: entry:
4848
// CHECK-NEXT: ret i32 0
4949
//
@@ -69,7 +69,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
6969
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
7070
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
7171
// CHECK: resolver_return:
72-
// CHECK-NEXT: ret ptr @ftc._MlseMaes
72+
// CHECK-NEXT: ret ptr @ftc._MaesMlse
7373
// CHECK: resolver_else:
7474
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
7575
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
@@ -89,7 +89,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
8989
//
9090
//
9191
// CHECK: Function Attrs: noinline nounwind optnone
92-
// CHECK-LABEL: @ftc_def._Msha2Mmemtag2(
92+
// CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
9393
// CHECK-NEXT: entry:
9494
// CHECK-NEXT: ret i32 1
9595
//
@@ -109,7 +109,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
109109
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
110110
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
111111
// CHECK: resolver_return:
112-
// CHECK-NEXT: ret ptr @ftc_def._Msha2Mmemtag2
112+
// CHECK-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
113113
// CHECK: resolver_else:
114114
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
115115
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
@@ -155,7 +155,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
155155
//
156156
//
157157
// CHECK: Function Attrs: noinline nounwind optnone
158-
// CHECK-LABEL: @ftc_dup2._MdotprodMcrc(
158+
// CHECK-LABEL: @ftc_dup2._McrcMdotprod(
159159
// CHECK-NEXT: entry:
160160
// CHECK-NEXT: ret i32 3
161161
//
@@ -175,7 +175,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
175175
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
176176
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
177177
// CHECK: resolver_return:
178-
// CHECK-NEXT: ret ptr @ftc_dup2._MdotprodMcrc
178+
// CHECK-NEXT: ret ptr @ftc_dup2._McrcMdotprod
179179
// CHECK: resolver_else:
180180
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
181181
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256
@@ -239,7 +239,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
239239
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
240240
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
241241
// CHECK: resolver_return1:
242-
// CHECK-NEXT: ret ptr @ftc_inline1._MrcpcMpredres
242+
// CHECK-NEXT: ret ptr @ftc_inline1._MpredresMrcpc
243243
// CHECK: resolver_else2:
244244
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
245245
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 513
@@ -283,7 +283,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
283283
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
284284
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
285285
// CHECK: resolver_return:
286-
// CHECK-NEXT: ret ptr @ftc_inline3._MsveMsb
286+
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
287287
// CHECK: resolver_else:
288288
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
289289
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
@@ -303,7 +303,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
303303
//
304304
//
305305
// CHECK: Function Attrs: noinline nounwind optnone
306-
// CHECK-LABEL: @ftc_inline1._MrcpcMpredres(
306+
// CHECK-LABEL: @ftc_inline1._MpredresMrcpc(
307307
// CHECK-NEXT: entry:
308308
// CHECK-NEXT: ret i32 1
309309
//
@@ -345,7 +345,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
345345
//
346346
//
347347
// CHECK: Function Attrs: noinline nounwind optnone
348-
// CHECK-LABEL: @ftc_inline3._MsveMsb(
348+
// CHECK-LABEL: @ftc_inline3._MsbMsve(
349349
// CHECK-NEXT: entry:
350350
// CHECK-NEXT: ret i32 3
351351
//

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 23 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -102,14 +102,14 @@ int hoo(void) {
102102
// CHECK: @fmv_c = weak_odr ifunc void (), ptr @fmv_c.resolver
103103
//.
104104
// CHECK: Function Attrs: noinline nounwind optnone
105-
// CHECK-LABEL: define {{[^@]+}}@fmv._MrngMflagmMfp16fml
105+
// CHECK-LABEL: define {{[^@]+}}@fmv._MflagmMfp16fmlMrng
106106
// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
107107
// CHECK-NEXT: entry:
108108
// CHECK-NEXT: ret i32 1
109109
//
110110
//
111111
// CHECK: Function Attrs: noinline nounwind optnone
112-
// CHECK-LABEL: define {{[^@]+}}@fmv_one._MsimdMls64
112+
// CHECK-LABEL: define {{[^@]+}}@fmv_one._Mls64Msimd
113113
// CHECK-SAME: () #[[ATTR1:[0-9]+]] {
114114
// CHECK-NEXT: entry:
115115
// CHECK-NEXT: ret i32 1
@@ -143,7 +143,7 @@ int hoo(void) {
143143
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
144144
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
145145
// CHECK: resolver_return:
146-
// CHECK-NEXT: ret ptr @fmv._MrngMflagmMfp16fml
146+
// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng
147147
// CHECK: resolver_else:
148148
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
149149
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72057594037927940
@@ -183,7 +183,7 @@ int hoo(void) {
183183
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
184184
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
185185
// CHECK: resolver_return9:
186-
// CHECK-NEXT: ret ptr @fmv._MfpMaes
186+
// CHECK-NEXT: ret ptr @fmv._MaesMfp
187187
// CHECK: resolver_else10:
188188
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
189189
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 4224
@@ -214,12 +214,12 @@ int hoo(void) {
214214
//
215215
// CHECK-LABEL: define {{[^@]+}}@fmv_one.resolver() comdat {
216216
// CHECK-NEXT: resolver_entry:
217-
// CHECK-NEXT: ret ptr @fmv_one._MsimdMls64
217+
// CHECK-NEXT: ret ptr @fmv_one._Mls64Msimd
218218
//
219219
//
220220
// CHECK-LABEL: define {{[^@]+}}@fmv_two.resolver() comdat {
221221
// CHECK-NEXT: resolver_entry:
222-
// CHECK-NEXT: ret ptr @fmv_two._MsimdMfp16
222+
// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd
223223
//
224224
//
225225
// CHECK-LABEL: define {{[^@]+}}@fmv_e.resolver() comdat {
@@ -262,47 +262,47 @@ int hoo(void) {
262262
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
263263
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
264264
// CHECK: resolver_return:
265-
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16Mfp16MfcmaMsme
265+
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16Mfp16Msme
266266
// CHECK: resolver_else:
267267
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
268268
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 893353197568
269269
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 893353197568
270270
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
271271
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
272272
// CHECK: resolver_return1:
273-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-pmull128Msve2-bitperm
273+
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
274274
// CHECK: resolver_else2:
275275
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
276276
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 34359773184
277277
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 34359773184
278278
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
279279
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
280280
// CHECK: resolver_return3:
281-
// CHECK-NEXT: ret ptr @fmv_inline._Msha1MpmullMf64mm
281+
// CHECK-NEXT: ret ptr @fmv_inline._Mf64mmMpmullMsha1
282282
// CHECK: resolver_else4:
283283
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
284284
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 17246986240
285285
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 17246986240
286286
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
287287
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
288288
// CHECK: resolver_return5:
289-
// CHECK-NEXT: ret ptr @fmv_inline._Msha3Mi8mmMf32mm
289+
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
290290
// CHECK: resolver_else6:
291291
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
292292
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 288265560523800576
293293
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 288265560523800576
294294
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
295295
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
296296
// CHECK: resolver_return7:
297-
// CHECK-NEXT: ret ptr @fmv_inline._Mrcpc3Mmemtag3
297+
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag3Mrcpc3
298298
// CHECK: resolver_else8:
299299
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
300300
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 19791209299968
301301
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19791209299968
302302
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
303303
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
304304
// CHECK: resolver_return9:
305-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-sm4Mmemtag2
305+
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag2Msve2-sm4
306306
// CHECK: resolver_else10:
307307
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
308308
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1236950581248
@@ -334,7 +334,7 @@ int hoo(void) {
334334
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
335335
// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
336336
// CHECK: resolver_return17:
337-
// CHECK-NEXT: ret ptr @fmv_inline._MrcpcMfrintts
337+
// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc
338338
// CHECK: resolver_else18:
339339
// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
340340
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 8650752
@@ -448,7 +448,7 @@ int hoo(void) {
448448
//
449449
//
450450
// CHECK: Function Attrs: noinline nounwind optnone
451-
// CHECK-LABEL: define {{[^@]+}}@fmv._MfpMaes
451+
// CHECK-LABEL: define {{[^@]+}}@fmv._MaesMfp
452452
// CHECK-SAME: () #[[ATTR1]] {
453453
// CHECK-NEXT: entry:
454454
// CHECK-NEXT: ret i32 6
@@ -511,7 +511,7 @@ int hoo(void) {
511511
//
512512
//
513513
// CHECK: Function Attrs: noinline nounwind optnone
514-
// CHECK-LABEL: define {{[^@]+}}@fmv_two._MsimdMfp16
514+
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd
515515
// CHECK-SAME: () #[[ATTR1]] {
516516
// CHECK-NEXT: entry:
517517
// CHECK-NEXT: ret i32 4
@@ -532,21 +532,21 @@ int hoo(void) {
532532
//
533533
//
534534
// CHECK: Function Attrs: noinline nounwind optnone
535-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msha1MpmullMf64mm
535+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha1
536536
// CHECK-SAME: () #[[ATTR12:[0-9]+]] {
537537
// CHECK-NEXT: entry:
538538
// CHECK-NEXT: ret i32 1
539539
//
540540
//
541541
// CHECK: Function Attrs: noinline nounwind optnone
542-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16Mfp16MfcmaMsme
542+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16Mfp16Msme
543543
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
544544
// CHECK-NEXT: entry:
545545
// CHECK-NEXT: ret i32 2
546546
//
547547
//
548548
// CHECK: Function Attrs: noinline nounwind optnone
549-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msha3Mi8mmMf32mm
549+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3
550550
// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
551551
// CHECK-NEXT: entry:
552552
// CHECK-NEXT: ret i32 12
@@ -574,7 +574,7 @@ int hoo(void) {
574574
//
575575
//
576576
// CHECK: Function Attrs: noinline nounwind optnone
577-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MrcpcMfrintts
577+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc
578578
// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
579579
// CHECK-NEXT: entry:
580580
// CHECK-NEXT: ret i32 3
@@ -595,21 +595,21 @@ int hoo(void) {
595595
//
596596
//
597597
// CHECK: Function Attrs: noinline nounwind optnone
598-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-pmull128Msve2-bitperm
598+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
599599
// CHECK-SAME: () #[[ATTR21:[0-9]+]] {
600600
// CHECK-NEXT: entry:
601601
// CHECK-NEXT: ret i32 9
602602
//
603603
//
604604
// CHECK: Function Attrs: noinline nounwind optnone
605-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-sm4Mmemtag2
605+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag2Msve2-sm4
606606
// CHECK-SAME: () #[[ATTR22:[0-9]+]] {
607607
// CHECK-NEXT: entry:
608608
// CHECK-NEXT: ret i32 10
609609
//
610610
//
611611
// CHECK: Function Attrs: noinline nounwind optnone
612-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mrcpc3Mmemtag3
612+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag3Mrcpc3
613613
// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
614614
// CHECK-NEXT: entry:
615615
// CHECK-NEXT: ret i32 11
@@ -785,5 +785,4 @@ int hoo(void) {
785785
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
786786
//.
787787
// CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
788-
// CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
789-
//.
788+
// CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}

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