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3 | 3 |
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4 | 4 | ; rdar://5992453
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5 | 5 | ; A & 255
|
6 |
| -define i32 @test4(i32 %a) nounwind { |
| 6 | +define i32 @test4(i32 %a) { |
7 | 7 | ; CHECK-LABEL: @test4(
|
8 | 8 | ; CHECK-NEXT: [[T2:%.*]] = and i32 [[A:%.*]], 255
|
9 | 9 | ; CHECK-NEXT: ret i32 [[T2]]
|
10 | 10 | ;
|
11 |
| - %t2 = tail call i32 @llvm.bswap.i32( i32 %a ) |
| 11 | + %t2 = call i32 @llvm.bswap.i32( i32 %a ) |
12 | 12 | %t4 = lshr i32 %t2, 24
|
13 | 13 | ret i32 %t4
|
14 | 14 | }
|
15 | 15 |
|
16 | 16 | ; a >> 24
|
17 |
| -define i32 @test6(i32 %a) nounwind { |
| 17 | +define i32 @test6(i32 %a) { |
18 | 18 | ; CHECK-LABEL: @test6(
|
19 | 19 | ; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[A:%.*]], 24
|
20 | 20 | ; CHECK-NEXT: ret i32 [[T2]]
|
21 | 21 | ;
|
22 |
| - %t2 = tail call i32 @llvm.bswap.i32( i32 %a ) |
| 22 | + %t2 = call i32 @llvm.bswap.i32( i32 %a ) |
23 | 23 | %t4 = and i32 %t2, 255
|
24 | 24 | ret i32 %t4
|
25 | 25 | }
|
26 | 26 |
|
| 27 | +define i32 @lshr8_i32(i32 %x) { |
| 28 | +; CHECK-LABEL: @lshr8_i32( |
| 29 | +; CHECK-NEXT: [[S:%.*]] = lshr i32 [[X:%.*]], 8 |
| 30 | +; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.bswap.i32(i32 [[S]]) |
| 31 | +; CHECK-NEXT: ret i32 [[R]] |
| 32 | +; |
| 33 | + %s = lshr i32 %x, 8 |
| 34 | + %r = call i32 @llvm.bswap.i32(i32 %s) |
| 35 | + ret i32 %r |
| 36 | +} |
| 37 | + |
| 38 | +define <2 x i32> @lshr16_v2i32(<2 x i32> %x) { |
| 39 | +; CHECK-LABEL: @lshr16_v2i32( |
| 40 | +; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 16, i32 16> |
| 41 | +; CHECK-NEXT: [[R:%.*]] = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[S]]) |
| 42 | +; CHECK-NEXT: ret <2 x i32> [[R]] |
| 43 | +; |
| 44 | + %s = lshr <2 x i32> %x, <i32 16, i32 16> |
| 45 | + %r = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %s) |
| 46 | + ret <2 x i32> %r |
| 47 | +} |
| 48 | + |
| 49 | +define i32 @lshr24_i32(i32 %x) { |
| 50 | +; CHECK-LABEL: @lshr24_i32( |
| 51 | +; CHECK-NEXT: [[S:%.*]] = and i32 [[X:%.*]], -16777216 |
| 52 | +; CHECK-NEXT: ret i32 [[S]] |
| 53 | +; |
| 54 | + %s = lshr i32 %x, 24 |
| 55 | + %r = call i32 @llvm.bswap.i32(i32 %s) |
| 56 | + ret i32 %r |
| 57 | +} |
| 58 | + |
| 59 | +define i32 @lshr12_i32(i32 %x) { |
| 60 | +; CHECK-LABEL: @lshr12_i32( |
| 61 | +; CHECK-NEXT: [[S:%.*]] = lshr i32 [[X:%.*]], 12 |
| 62 | +; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.bswap.i32(i32 [[S]]) |
| 63 | +; CHECK-NEXT: ret i32 [[R]] |
| 64 | +; |
| 65 | + %s = lshr i32 %x, 12 |
| 66 | + %r = call i32 @llvm.bswap.i32(i32 %s) |
| 67 | + ret i32 %r |
| 68 | +} |
| 69 | + |
| 70 | +define i32 @lshr8_i32_use(i32 %x, i32* %p) { |
| 71 | +; CHECK-LABEL: @lshr8_i32_use( |
| 72 | +; CHECK-NEXT: [[S:%.*]] = lshr i32 [[X:%.*]], 12 |
| 73 | +; CHECK-NEXT: store i32 [[S]], i32* [[P:%.*]], align 4 |
| 74 | +; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.bswap.i32(i32 [[S]]) |
| 75 | +; CHECK-NEXT: ret i32 [[R]] |
| 76 | +; |
| 77 | + %s = lshr i32 %x, 12 |
| 78 | + store i32 %s, i32* %p |
| 79 | + %r = call i32 @llvm.bswap.i32(i32 %s) |
| 80 | + ret i32 %r |
| 81 | +} |
| 82 | + |
| 83 | +define i64 @shl16_i64(i64 %x) { |
| 84 | +; CHECK-LABEL: @shl16_i64( |
| 85 | +; CHECK-NEXT: [[S:%.*]] = shl i64 [[X:%.*]], 16 |
| 86 | +; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.bswap.i64(i64 [[S]]) |
| 87 | +; CHECK-NEXT: ret i64 [[R]] |
| 88 | +; |
| 89 | + %s = shl i64 %x, 16 |
| 90 | + %r = call i64 @llvm.bswap.i64(i64 %s) |
| 91 | + ret i64 %r |
| 92 | +} |
| 93 | + |
| 94 | +define <2 x i64> @shl16_v2i64(<2 x i64> %x) { |
| 95 | +; CHECK-LABEL: @shl16_v2i64( |
| 96 | +; CHECK-NEXT: [[S:%.*]] = shl <2 x i64> [[X:%.*]], <i64 poison, i64 24> |
| 97 | +; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> [[S]]) |
| 98 | +; CHECK-NEXT: ret <2 x i64> [[R]] |
| 99 | +; |
| 100 | + %s = shl <2 x i64> %x, <i64 poison, i64 24> |
| 101 | + %r = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %s) |
| 102 | + ret <2 x i64> %r |
| 103 | +} |
| 104 | + |
| 105 | +define i64 @shl56_i64(i64 %x) { |
| 106 | +; CHECK-LABEL: @shl56_i64( |
| 107 | +; CHECK-NEXT: [[S:%.*]] = and i64 [[X:%.*]], 255 |
| 108 | +; CHECK-NEXT: ret i64 [[S]] |
| 109 | +; |
| 110 | + %s = shl i64 %x, 56 |
| 111 | + %r = call i64 @llvm.bswap.i64(i64 %s) |
| 112 | + ret i64 %r |
| 113 | +} |
| 114 | + |
| 115 | +define i64 @shl42_i64(i64 %x) { |
| 116 | +; CHECK-LABEL: @shl42_i64( |
| 117 | +; CHECK-NEXT: [[S:%.*]] = shl i64 [[X:%.*]], 42 |
| 118 | +; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.bswap.i64(i64 [[S]]) |
| 119 | +; CHECK-NEXT: ret i64 [[R]] |
| 120 | +; |
| 121 | + %s = shl i64 %x, 42 |
| 122 | + %r = call i64 @llvm.bswap.i64(i64 %s) |
| 123 | + ret i64 %r |
| 124 | +} |
| 125 | + |
| 126 | +define i32 @shl8_i32_use(i32 %x, i32* %p) { |
| 127 | +; CHECK-LABEL: @shl8_i32_use( |
| 128 | +; CHECK-NEXT: [[S:%.*]] = shl i32 [[X:%.*]], 8 |
| 129 | +; CHECK-NEXT: store i32 [[S]], i32* [[P:%.*]], align 4 |
| 130 | +; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.bswap.i32(i32 [[S]]) |
| 131 | +; CHECK-NEXT: ret i32 [[R]] |
| 132 | +; |
| 133 | + %s = shl i32 %x, 8 |
| 134 | + store i32 %s, i32* %p |
| 135 | + %r = call i32 @llvm.bswap.i32(i32 %s) |
| 136 | + ret i32 %r |
| 137 | +} |
| 138 | + |
| 139 | +define i64 @swap_shl16_i64(i64 %x) { |
| 140 | +; CHECK-LABEL: @swap_shl16_i64( |
| 141 | +; CHECK-NEXT: [[B:%.*]] = call i64 @llvm.bswap.i64(i64 [[X:%.*]]) |
| 142 | +; CHECK-NEXT: [[S:%.*]] = shl i64 [[B]], 16 |
| 143 | +; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.bswap.i64(i64 [[S]]) |
| 144 | +; CHECK-NEXT: ret i64 [[R]] |
| 145 | +; |
| 146 | + %b = call i64 @llvm.bswap.i64(i64 %x) |
| 147 | + %s = shl i64 %b, 16 |
| 148 | + %r = call i64 @llvm.bswap.i64(i64 %s) |
| 149 | + ret i64 %r |
| 150 | +} |
| 151 | + |
27 | 152 | ; PR5284
|
28 | 153 | define i16 @test7(i32 %A) {
|
29 | 154 | ; CHECK-LABEL: @test7(
|
|
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