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release/20.x: [AArch64] Handle XAR with v1i64 operand types (llvm#141754)
When converting ROTR(XOR(a, b)) to XAR(a, b), or ROTR(a, a) to XAR(a, zero) we were not handling v1i64 types, meaning illegal copies get generated. This addresses that by generating insert_subreg and extract_subreg for v1i64 to keep the values with the correct types. Fixes llvm#141746
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llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4608,9 +4608,31 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
46084608
if (ShAmt + HsAmt != 64)
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return false;
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4611+
// If the input is a v1i64, widen to a v2i64 to use XAR.
4612+
assert((VT == MVT::v1i64 || VT == MVT::v2i64) && "Unexpected XAR type!");
4613+
if (VT == MVT::v1i64) {
4614+
EVT SVT = MVT::v2i64;
4615+
SDValue Undef =
4616+
SDValue(CurDAG->getMachineNode(AArch64::IMPLICIT_DEF, DL, SVT), 0);
4617+
SDValue DSub = CurDAG->getTargetConstant(AArch64::dsub, DL, MVT::i32);
4618+
R1 = SDValue(CurDAG->getMachineNode(AArch64::INSERT_SUBREG, DL, SVT, Undef,
4619+
R1, DSub),
4620+
0);
4621+
if (R2.getValueType() == MVT::v1i64)
4622+
R2 = SDValue(CurDAG->getMachineNode(AArch64::INSERT_SUBREG, DL, SVT,
4623+
Undef, R2, DSub),
4624+
0);
4625+
}
4626+
46114627
SDValue Ops[] = {R1, R2, Imm};
4612-
CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops);
4628+
SDNode *XAR = CurDAG->getMachineNode(AArch64::XAR, DL, MVT::v2i64, Ops);
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4630+
if (VT == MVT::v1i64) {
4631+
SDValue DSub = CurDAG->getTargetConstant(AArch64::dsub, DL, MVT::i32);
4632+
XAR = CurDAG->getMachineNode(AArch64::EXTRACT_SUBREG, DL, VT,
4633+
SDValue(XAR, 0), DSub);
4634+
}
4635+
ReplaceNode(N, XAR);
46144636
return true;
46154637
}
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llvm/test/CodeGen/AArch64/xar.ll

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,4 +19,24 @@ define <2 x i64> @xar(<2 x i64> %x, <2 x i64> %y) {
1919
ret <2 x i64> %b
2020
}
2121

22+
define <1 x i64> @xar_v1i64(<1 x i64> %a, <1 x i64> %b) {
23+
; SHA3-LABEL: xar_v1i64:
24+
; SHA3: // %bb.0:
25+
; SHA3-NEXT: // kill: def $d0 killed $d0 def $q0
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; SHA3-NEXT: // kill: def $d1 killed $d1 def $q1
27+
; SHA3-NEXT: xar v0.2d, v0.2d, v1.2d, #63
28+
; SHA3-NEXT: // kill: def $d0 killed $d0 killed $q0
29+
; SHA3-NEXT: ret
30+
;
31+
; NOSHA3-LABEL: xar_v1i64:
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; NOSHA3: // %bb.0:
33+
; NOSHA3-NEXT: eor v1.8b, v0.8b, v1.8b
34+
; NOSHA3-NEXT: shl d0, d1, #1
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; NOSHA3-NEXT: usra d0, d1, #63
36+
; NOSHA3-NEXT: ret
37+
%v.val = xor <1 x i64> %a, %b
38+
%fshl = tail call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %v.val, <1 x i64> %v.val, <1 x i64> splat (i64 1))
39+
ret <1 x i64> %fshl
40+
}
41+
2242
declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)

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