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[CodeGen] Provide a target independent default for optimizeLoadInst [NFC]
This just moves the x86 implementation into generic code since it appears to be suitable for any target. The heart of this transform is inside foldMemoryOperand so other targets won't actually kick in until they implement said API. This just removes one piece to implement in the process of enabling foldMemoryOperand.
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4 files changed

+42
-49
lines changed

4 files changed

+42
-49
lines changed

llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1791,9 +1791,7 @@ class TargetInstrInfo : public MCInstrInfo {
17911791
virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
17921792
const MachineRegisterInfo *MRI,
17931793
Register &FoldAsLoadDefReg,
1794-
MachineInstr *&DefMI) const {
1795-
return nullptr;
1796-
}
1794+
MachineInstr *&DefMI) const;
17971795

17981796
/// 'Reg' is known to be defined by a move immediate instruction,
17991797
/// try to fold the immediate into the use instruction.

llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -496,6 +496,47 @@ static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
496496

497497
MCInst TargetInstrInfo::getNop() const { llvm_unreachable("Not implemented"); }
498498

499+
/// Try to remove the load by folding it to a register
500+
/// operand at the use. We fold the load instructions if load defines a virtual
501+
/// register, the virtual register is used once in the same BB, and the
502+
/// instructions in-between do not load or store, and have no side effects.
503+
MachineInstr *TargetInstrInfo::optimizeLoadInstr(MachineInstr &MI,
504+
const MachineRegisterInfo *MRI,
505+
Register &FoldAsLoadDefReg,
506+
MachineInstr *&DefMI) const {
507+
// Check whether we can move DefMI here.
508+
DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
509+
assert(DefMI);
510+
bool SawStore = false;
511+
if (!DefMI->isSafeToMove(SawStore))
512+
return nullptr;
513+
514+
// Collect information about virtual register operands of MI.
515+
SmallVector<unsigned, 1> SrcOperandIds;
516+
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
517+
MachineOperand &MO = MI.getOperand(i);
518+
if (!MO.isReg())
519+
continue;
520+
Register Reg = MO.getReg();
521+
if (Reg != FoldAsLoadDefReg)
522+
continue;
523+
// Do not fold if we have a subreg use or a def.
524+
if (MO.getSubReg() || MO.isDef())
525+
return nullptr;
526+
SrcOperandIds.push_back(i);
527+
}
528+
if (SrcOperandIds.empty())
529+
return nullptr;
530+
531+
// Check whether we can fold the def into SrcOperandId.
532+
if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
533+
FoldAsLoadDefReg = 0;
534+
return FoldMI;
535+
}
536+
537+
return nullptr;
538+
}
539+
499540
std::pair<unsigned, unsigned>
500541
TargetInstrInfo::getPatchpointUnfoldableRange(const MachineInstr &MI) const {
501542
switch (MI.getOpcode()) {

llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 0 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -5716,47 +5716,6 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
57165716
return true;
57175717
}
57185718

5719-
/// Try to remove the load by folding it to a register
5720-
/// operand at the use. We fold the load instructions if load defines a virtual
5721-
/// register, the virtual register is used once in the same BB, and the
5722-
/// instructions in-between do not load or store, and have no side effects.
5723-
MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
5724-
const MachineRegisterInfo *MRI,
5725-
Register &FoldAsLoadDefReg,
5726-
MachineInstr *&DefMI) const {
5727-
// Check whether we can move DefMI here.
5728-
DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5729-
assert(DefMI);
5730-
bool SawStore = false;
5731-
if (!DefMI->isSafeToMove(SawStore))
5732-
return nullptr;
5733-
5734-
// Collect information about virtual register operands of MI.
5735-
SmallVector<unsigned, 1> SrcOperandIds;
5736-
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5737-
MachineOperand &MO = MI.getOperand(i);
5738-
if (!MO.isReg())
5739-
continue;
5740-
Register Reg = MO.getReg();
5741-
if (Reg != FoldAsLoadDefReg)
5742-
continue;
5743-
// Do not fold if we have a subreg use or a def.
5744-
if (MO.getSubReg() || MO.isDef())
5745-
return nullptr;
5746-
SrcOperandIds.push_back(i);
5747-
}
5748-
if (SrcOperandIds.empty())
5749-
return nullptr;
5750-
5751-
// Check whether we can fold the def into SrcOperandId.
5752-
if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
5753-
FoldAsLoadDefReg = 0;
5754-
return FoldMI;
5755-
}
5756-
5757-
return nullptr;
5758-
}
5759-
57605719
/// \returns true if the instruction can be changed to COPY when imm is 0.
57615720
static bool canConvert2Copy(unsigned Opc) {
57625721
switch (Opc) {

llvm/lib/Target/X86/X86InstrInfo.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -571,11 +571,6 @@ class X86InstrInfo final : public X86GenInstrInfo {
571571
Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
572572
const MachineRegisterInfo *MRI) const override;
573573

574-
MachineInstr *optimizeLoadInstr(MachineInstr &MI,
575-
const MachineRegisterInfo *MRI,
576-
Register &FoldAsLoadDefReg,
577-
MachineInstr *&DefMI) const override;
578-
579574
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
580575
MachineRegisterInfo *MRI) const override;
581576

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