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[mlir][SME] Re-order patterns alphabetically (nfc)
1 parent c87b2c9 commit 23b5f92

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2 files changed

+9
-11
lines changed

2 files changed

+9
-11
lines changed

mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -431,9 +431,8 @@ struct TransposeOpToArmSMELowering
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432432
void mlir::populateVectorToArmSMEPatterns(RewritePatternSet &patterns,
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MLIRContext &ctx) {
434-
patterns.add<TransferReadPermutationToArmSMELowering,
435-
TransferWriteToArmSMELowering, VectorLoadToArmSMELowering,
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VectorStoreToArmSMELowering, ConstantOpToArmSMELowering,
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BroadcastOpToArmSMELowering, SplatOpToArmSMELowering,
438-
TransposeOpToArmSMELowering>(&ctx);
434+
patterns.add<BroadcastOpToArmSMELowering, ConstantOpToArmSMELowering,
435+
SplatOpToArmSMELowering, TransferReadPermutationToArmSMELowering,
436+
TransferWriteToArmSMELowering, TransposeOpToArmSMELowering,
437+
VectorLoadToArmSMELowering, VectorStoreToArmSMELowering>(&ctx);
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}

mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -600,10 +600,9 @@ void mlir::configureArmSMELegalizeForExportTarget(
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601601
void mlir::populateArmSMELegalizeForLLVMExportPatterns(
602602
LLVMTypeConverter &converter, RewritePatternSet &patterns) {
603-
patterns.add<EnableZAPattern, DisableZAPattern>(patterns.getContext());
604-
patterns
605-
.add<ZeroOpConversion, StoreTileSliceToArmSMELowering,
606-
LoadTileSliceToArmSMELowering, MoveTileSliceToVectorArmSMELowering,
607-
MoveVectorToTileSliceToArmSMELowering,
608-
VectorOuterProductToArmSMELowering>(converter);
603+
patterns.add<DisableZAPattern, EnableZAPattern>(patterns.getContext());
604+
patterns.add<
605+
LoadTileSliceToArmSMELowering, MoveTileSliceToVectorArmSMELowering,
606+
MoveVectorToTileSliceToArmSMELowering, StoreTileSliceToArmSMELowering,
607+
VectorOuterProductToArmSMELowering, ZeroOpConversion>(converter);
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}

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