[NFC][Test][PowerPC] Add one test to verify the behavior of vector

mul/add for v8i16

Author: QingShan Zhang

llvm/test/CodeGen/PowerPC/vmladduhm.ll

@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P9
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P8
+define <8 x i16> @mul(<8 x i16> %m, <8 x i16> %n) {
+; CHECK-LABEL: mul:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxlxor 36, 36, 36
+; CHECK-NEXT:    vmladduhm 2, 2, 3, 4
+; CHECK-NEXT:    blr
+entry:
+  %0 = mul <8 x i16> %m, %n
+  ret <8 x i16> %0
+}
+
+define <8 x i16> @madd(<8 x i16> %m, <8 x i16> %n, <8 x i16> %o) {
+; CHECK-LABEL: madd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxlxor 37, 37, 37
+; CHECK-NEXT:    vmladduhm 2, 2, 3, 5
+; CHECK-NEXT:    vadduhm 2, 2, 4
+; CHECK-NEXT:    blr
+entry:
+  %0 = mul <8 x i16> %m, %n
+  %1 = add <8 x i16> %0, %o
+  ret <8 x i16> %1
+}