Skip to content

Commit 24e8c6a

Browse files
lukel97lukel97
authored
[RISCV] Convert remaining constant splats in tests to use splat shorthand. NFC (llvm#88099)
This follows on from llvm#87616, but includes the tests with codegen differences. These are presumably due to the fact that the splat is now a constant expression. They don't seem to affect anything that we were specifically testing for.
1 parent 4ae33c5 commit 24e8c6a

28 files changed

+726
-2387
lines changed

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Lines changed: 513 additions & 1770 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

Lines changed: 85 additions & 409 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1349,16 +1349,16 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
13491349
; RV32-LABEL: vadd_vx_v32i64:
13501350
; RV32: # %bb.0:
13511351
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1352-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1353-
; RV32-NEXT: li a1, 32
1354-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
13551352
; RV32-NEXT: li a2, 16
1356-
; RV32-NEXT: vmv.v.i v24, -1
1353+
; RV32-NEXT: vslidedown.vi v7, v0, 2
13571354
; RV32-NEXT: mv a1, a0
13581355
; RV32-NEXT: bltu a0, a2, .LBB108_2
13591356
; RV32-NEXT: # %bb.1:
13601357
; RV32-NEXT: li a1, 16
13611358
; RV32-NEXT: .LBB108_2:
1359+
; RV32-NEXT: li a2, 32
1360+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1361+
; RV32-NEXT: vmv.v.i v24, -1
13621362
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
13631363
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
13641364
; RV32-NEXT: addi a1, a0, -16
@@ -1390,24 +1390,22 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
13901390
; RV64-NEXT: vmv1r.v v0, v24
13911391
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
13921392
; RV64-NEXT: ret
1393-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1394-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1395-
%v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1393+
%v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
13961394
ret <32 x i64> %v
13971395
}
13981396

13991397
define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14001398
; RV32-LABEL: vadd_vi_v32i64_unmasked:
14011399
; RV32: # %bb.0:
1402-
; RV32-NEXT: li a1, 32
1403-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
14041400
; RV32-NEXT: li a2, 16
1405-
; RV32-NEXT: vmv.v.i v24, -1
14061401
; RV32-NEXT: mv a1, a0
14071402
; RV32-NEXT: bltu a0, a2, .LBB109_2
14081403
; RV32-NEXT: # %bb.1:
14091404
; RV32-NEXT: li a1, 16
14101405
; RV32-NEXT: .LBB109_2:
1406+
; RV32-NEXT: li a2, 32
1407+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1408+
; RV32-NEXT: vmv.v.i v24, -1
14111409
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
14121410
; RV32-NEXT: vadd.vv v8, v8, v24
14131411
; RV32-NEXT: addi a1, a0, -16
@@ -1435,11 +1433,7 @@ define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14351433
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
14361434
; RV64-NEXT: vadd.vi v16, v16, -1
14371435
; RV64-NEXT: ret
1438-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1439-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1440-
%head = insertelement <32 x i1> poison, i1 true, i32 0
1441-
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
1442-
%v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1436+
%v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
14431437
ret <32 x i64> %v
14441438
}
14451439

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1022,16 +1022,16 @@ define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
10221022
; RV32-LABEL: vmax_vx_v32i64:
10231023
; RV32: # %bb.0:
10241024
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1025-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1026-
; RV32-NEXT: li a1, 32
1027-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
10281025
; RV32-NEXT: li a2, 16
1029-
; RV32-NEXT: vmv.v.i v24, -1
1026+
; RV32-NEXT: vslidedown.vi v7, v0, 2
10301027
; RV32-NEXT: mv a1, a0
10311028
; RV32-NEXT: bltu a0, a2, .LBB74_2
10321029
; RV32-NEXT: # %bb.1:
10331030
; RV32-NEXT: li a1, 16
10341031
; RV32-NEXT: .LBB74_2:
1032+
; RV32-NEXT: li a2, 32
1033+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1034+
; RV32-NEXT: vmv.v.i v24, -1
10351035
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
10361036
; RV32-NEXT: vmax.vv v8, v8, v24, v0.t
10371037
; RV32-NEXT: addi a1, a0, -16
@@ -1064,8 +1064,6 @@ define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
10641064
; RV64-NEXT: vmv1r.v v0, v24
10651065
; RV64-NEXT: vmax.vx v16, v16, a2, v0.t
10661066
; RV64-NEXT: ret
1067-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1068-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1069-
%v = call <32 x i64> @llvm.vp.smax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1067+
%v = call <32 x i64> @llvm.vp.smax.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
10701068
ret <32 x i64> %v
10711069
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1021,16 +1021,16 @@ define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
10211021
; RV32-LABEL: vmaxu_vx_v32i64:
10221022
; RV32: # %bb.0:
10231023
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1024-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1025-
; RV32-NEXT: li a1, 32
1026-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
10271024
; RV32-NEXT: li a2, 16
1028-
; RV32-NEXT: vmv.v.i v24, -1
1025+
; RV32-NEXT: vslidedown.vi v7, v0, 2
10291026
; RV32-NEXT: mv a1, a0
10301027
; RV32-NEXT: bltu a0, a2, .LBB74_2
10311028
; RV32-NEXT: # %bb.1:
10321029
; RV32-NEXT: li a1, 16
10331030
; RV32-NEXT: .LBB74_2:
1031+
; RV32-NEXT: li a2, 32
1032+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1033+
; RV32-NEXT: vmv.v.i v24, -1
10341034
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
10351035
; RV32-NEXT: vmaxu.vv v8, v8, v24, v0.t
10361036
; RV32-NEXT: addi a1, a0, -16
@@ -1063,8 +1063,6 @@ define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
10631063
; RV64-NEXT: vmv1r.v v0, v24
10641064
; RV64-NEXT: vmaxu.vx v16, v16, a2, v0.t
10651065
; RV64-NEXT: ret
1066-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1067-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1068-
%v = call <32 x i64> @llvm.vp.umax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1066+
%v = call <32 x i64> @llvm.vp.umax.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
10691067
ret <32 x i64> %v
10701068
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1022,16 +1022,16 @@ define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
10221022
; RV32-LABEL: vmin_vx_v32i64:
10231023
; RV32: # %bb.0:
10241024
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1025-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1026-
; RV32-NEXT: li a1, 32
1027-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
10281025
; RV32-NEXT: li a2, 16
1029-
; RV32-NEXT: vmv.v.i v24, -1
1026+
; RV32-NEXT: vslidedown.vi v7, v0, 2
10301027
; RV32-NEXT: mv a1, a0
10311028
; RV32-NEXT: bltu a0, a2, .LBB74_2
10321029
; RV32-NEXT: # %bb.1:
10331030
; RV32-NEXT: li a1, 16
10341031
; RV32-NEXT: .LBB74_2:
1032+
; RV32-NEXT: li a2, 32
1033+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1034+
; RV32-NEXT: vmv.v.i v24, -1
10351035
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
10361036
; RV32-NEXT: vmin.vv v8, v8, v24, v0.t
10371037
; RV32-NEXT: addi a1, a0, -16
@@ -1064,8 +1064,6 @@ define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
10641064
; RV64-NEXT: vmv1r.v v0, v24
10651065
; RV64-NEXT: vmin.vx v16, v16, a2, v0.t
10661066
; RV64-NEXT: ret
1067-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1068-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1069-
%v = call <32 x i64> @llvm.vp.smin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1067+
%v = call <32 x i64> @llvm.vp.smin.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
10701068
ret <32 x i64> %v
10711069
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1021,16 +1021,16 @@ define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
10211021
; RV32-LABEL: vminu_vx_v32i64:
10221022
; RV32: # %bb.0:
10231023
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1024-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1025-
; RV32-NEXT: li a1, 32
1026-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
10271024
; RV32-NEXT: li a2, 16
1028-
; RV32-NEXT: vmv.v.i v24, -1
1025+
; RV32-NEXT: vslidedown.vi v7, v0, 2
10291026
; RV32-NEXT: mv a1, a0
10301027
; RV32-NEXT: bltu a0, a2, .LBB74_2
10311028
; RV32-NEXT: # %bb.1:
10321029
; RV32-NEXT: li a1, 16
10331030
; RV32-NEXT: .LBB74_2:
1031+
; RV32-NEXT: li a2, 32
1032+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1033+
; RV32-NEXT: vmv.v.i v24, -1
10341034
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
10351035
; RV32-NEXT: vminu.vv v8, v8, v24, v0.t
10361036
; RV32-NEXT: addi a1, a0, -16
@@ -1063,8 +1063,6 @@ define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
10631063
; RV64-NEXT: vmv1r.v v0, v24
10641064
; RV64-NEXT: vminu.vx v16, v16, a2, v0.t
10651065
; RV64-NEXT: ret
1066-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1067-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1068-
%v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1066+
%v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
10691067
ret <32 x i64> %v
10701068
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1362,16 +1362,16 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
13621362
; RV32-LABEL: vsadd_vx_v32i64:
13631363
; RV32: # %bb.0:
13641364
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1365-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1366-
; RV32-NEXT: li a1, 32
1367-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
13681365
; RV32-NEXT: li a2, 16
1369-
; RV32-NEXT: vmv.v.i v24, -1
1366+
; RV32-NEXT: vslidedown.vi v7, v0, 2
13701367
; RV32-NEXT: mv a1, a0
13711368
; RV32-NEXT: bltu a0, a2, .LBB108_2
13721369
; RV32-NEXT: # %bb.1:
13731370
; RV32-NEXT: li a1, 16
13741371
; RV32-NEXT: .LBB108_2:
1372+
; RV32-NEXT: li a2, 32
1373+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1374+
; RV32-NEXT: vmv.v.i v24, -1
13751375
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
13761376
; RV32-NEXT: vsadd.vv v8, v8, v24, v0.t
13771377
; RV32-NEXT: addi a1, a0, -16
@@ -1403,24 +1403,22 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
14031403
; RV64-NEXT: vmv1r.v v0, v24
14041404
; RV64-NEXT: vsadd.vi v16, v16, -1, v0.t
14051405
; RV64-NEXT: ret
1406-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1407-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1408-
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1406+
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
14091407
ret <32 x i64> %v
14101408
}
14111409

14121410
define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14131411
; RV32-LABEL: vsadd_vi_v32i64_unmasked:
14141412
; RV32: # %bb.0:
1415-
; RV32-NEXT: li a1, 32
1416-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
14171413
; RV32-NEXT: li a2, 16
1418-
; RV32-NEXT: vmv.v.i v24, -1
14191414
; RV32-NEXT: mv a1, a0
14201415
; RV32-NEXT: bltu a0, a2, .LBB109_2
14211416
; RV32-NEXT: # %bb.1:
14221417
; RV32-NEXT: li a1, 16
14231418
; RV32-NEXT: .LBB109_2:
1419+
; RV32-NEXT: li a2, 32
1420+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1421+
; RV32-NEXT: vmv.v.i v24, -1
14241422
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
14251423
; RV32-NEXT: vsadd.vv v8, v8, v24
14261424
; RV32-NEXT: addi a1, a0, -16
@@ -1448,11 +1446,7 @@ define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14481446
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
14491447
; RV64-NEXT: vsadd.vi v16, v16, -1
14501448
; RV64-NEXT: ret
1451-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1452-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1453-
%head = insertelement <32 x i1> poison, i1 true, i32 0
1454-
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
1455-
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1449+
%v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
14561450
ret <32 x i64> %v
14571451
}
14581452

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1358,16 +1358,16 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
13581358
; RV32-LABEL: vsaddu_vx_v32i64:
13591359
; RV32: # %bb.0:
13601360
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1361-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1362-
; RV32-NEXT: li a1, 32
1363-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
13641361
; RV32-NEXT: li a2, 16
1365-
; RV32-NEXT: vmv.v.i v24, -1
1362+
; RV32-NEXT: vslidedown.vi v7, v0, 2
13661363
; RV32-NEXT: mv a1, a0
13671364
; RV32-NEXT: bltu a0, a2, .LBB108_2
13681365
; RV32-NEXT: # %bb.1:
13691366
; RV32-NEXT: li a1, 16
13701367
; RV32-NEXT: .LBB108_2:
1368+
; RV32-NEXT: li a2, 32
1369+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1370+
; RV32-NEXT: vmv.v.i v24, -1
13711371
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
13721372
; RV32-NEXT: vsaddu.vv v8, v8, v24, v0.t
13731373
; RV32-NEXT: addi a1, a0, -16
@@ -1399,24 +1399,22 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
13991399
; RV64-NEXT: vmv1r.v v0, v24
14001400
; RV64-NEXT: vsaddu.vi v16, v16, -1, v0.t
14011401
; RV64-NEXT: ret
1402-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1403-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1404-
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1402+
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
14051403
ret <32 x i64> %v
14061404
}
14071405

14081406
define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14091407
; RV32-LABEL: vsaddu_vi_v32i64_unmasked:
14101408
; RV32: # %bb.0:
1411-
; RV32-NEXT: li a1, 32
1412-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
14131409
; RV32-NEXT: li a2, 16
1414-
; RV32-NEXT: vmv.v.i v24, -1
14151410
; RV32-NEXT: mv a1, a0
14161411
; RV32-NEXT: bltu a0, a2, .LBB109_2
14171412
; RV32-NEXT: # %bb.1:
14181413
; RV32-NEXT: li a1, 16
14191414
; RV32-NEXT: .LBB109_2:
1415+
; RV32-NEXT: li a2, 32
1416+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1417+
; RV32-NEXT: vmv.v.i v24, -1
14201418
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
14211419
; RV32-NEXT: vsaddu.vv v8, v8, v24
14221420
; RV32-NEXT: addi a1, a0, -16
@@ -1444,11 +1442,7 @@ define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14441442
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
14451443
; RV64-NEXT: vsaddu.vi v16, v16, -1
14461444
; RV64-NEXT: ret
1447-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1448-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1449-
%head = insertelement <32 x i1> poison, i1 true, i32 0
1450-
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
1451-
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1445+
%v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
14521446
ret <32 x i64> %v
14531447
}
14541448

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1402,16 +1402,16 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
14021402
; RV32-LABEL: vssub_vx_v32i64:
14031403
; RV32: # %bb.0:
14041404
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
1405-
; RV32-NEXT: vslidedown.vi v7, v0, 2
1406-
; RV32-NEXT: li a1, 32
1407-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
14081405
; RV32-NEXT: li a2, 16
1409-
; RV32-NEXT: vmv.v.i v24, -1
1406+
; RV32-NEXT: vslidedown.vi v7, v0, 2
14101407
; RV32-NEXT: mv a1, a0
14111408
; RV32-NEXT: bltu a0, a2, .LBB108_2
14121409
; RV32-NEXT: # %bb.1:
14131410
; RV32-NEXT: li a1, 16
14141411
; RV32-NEXT: .LBB108_2:
1412+
; RV32-NEXT: li a2, 32
1413+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1414+
; RV32-NEXT: vmv.v.i v24, -1
14151415
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
14161416
; RV32-NEXT: vssub.vv v8, v8, v24, v0.t
14171417
; RV32-NEXT: addi a1, a0, -16
@@ -1444,24 +1444,22 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
14441444
; RV64-NEXT: vmv1r.v v0, v24
14451445
; RV64-NEXT: vssub.vx v16, v16, a2, v0.t
14461446
; RV64-NEXT: ret
1447-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1448-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1449-
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1447+
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
14501448
ret <32 x i64> %v
14511449
}
14521450

14531451
define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14541452
; RV32-LABEL: vssub_vi_v32i64_unmasked:
14551453
; RV32: # %bb.0:
1456-
; RV32-NEXT: li a1, 32
1457-
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
14581454
; RV32-NEXT: li a2, 16
1459-
; RV32-NEXT: vmv.v.i v24, -1
14601455
; RV32-NEXT: mv a1, a0
14611456
; RV32-NEXT: bltu a0, a2, .LBB109_2
14621457
; RV32-NEXT: # %bb.1:
14631458
; RV32-NEXT: li a1, 16
14641459
; RV32-NEXT: .LBB109_2:
1460+
; RV32-NEXT: li a2, 32
1461+
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
1462+
; RV32-NEXT: vmv.v.i v24, -1
14651463
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
14661464
; RV32-NEXT: vssub.vv v8, v8, v24
14671465
; RV32-NEXT: addi a1, a0, -16
@@ -1490,11 +1488,7 @@ define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
14901488
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
14911489
; RV64-NEXT: vssub.vx v16, v16, a2
14921490
; RV64-NEXT: ret
1493-
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
1494-
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
1495-
%head = insertelement <32 x i1> poison, i1 true, i32 0
1496-
%m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer
1497-
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
1491+
%v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
14981492
ret <32 x i64> %v
14991493
}
15001494

0 commit comments

Comments
 (0)