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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 |
| 2 | +; RUN: opt < %s -S -msan-check-access-address=0 -passes="msan" 2>&1 | FileCheck %s |
| 3 | + |
| 4 | +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" |
| 5 | +target triple = "x86_64-unknown-linux-gnu" |
| 6 | + |
| 7 | +define void @test_load_store_i32(ptr %a, ptr %b) sanitize_memory { |
| 8 | +; CHECK-LABEL: define void @test_load_store_i32( |
| 9 | +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] { |
| 10 | +; CHECK-NEXT: call void @llvm.donothing() |
| 11 | +; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x i32>, ptr [[A]], align 16 |
| 12 | +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 |
| 13 | +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 |
| 14 | +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr |
| 15 | +; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 16 |
| 16 | +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64 |
| 17 | +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 |
| 18 | +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr |
| 19 | +; CHECK-NEXT: store <vscale x 4 x i32> [[_MSLD]], ptr [[TMP7]], align 16 |
| 20 | +; CHECK-NEXT: store <vscale x 4 x i32> [[TMP1]], ptr [[B]], align 16 |
| 21 | +; CHECK-NEXT: ret void |
| 22 | +; |
| 23 | + %1 = load <vscale x 4 x i32>, ptr %a |
| 24 | + store <vscale x 4 x i32> %1, ptr %b |
| 25 | + ret void |
| 26 | +} |
| 27 | + |
| 28 | +define void @test_load_store_add_int(ptr %a, ptr %b) sanitize_memory { |
| 29 | +; CHECK-LABEL: define void @test_load_store_add_int( |
| 30 | +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { |
| 31 | +; CHECK-NEXT: call void @llvm.donothing() |
| 32 | +; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 8 x i64>, ptr [[A]], align 64 |
| 33 | +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 |
| 34 | +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 |
| 35 | +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr |
| 36 | +; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 8 x i64>, ptr [[TMP4]], align 64 |
| 37 | +; CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 8 x i64>, ptr [[B]], align 64 |
| 38 | +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[B]] to i64 |
| 39 | +; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080 |
| 40 | +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr |
| 41 | +; CHECK-NEXT: [[_MSLD1:%.*]] = load <vscale x 8 x i64>, ptr [[TMP8]], align 64 |
| 42 | +; CHECK-NEXT: [[_MSPROP:%.*]] = or <vscale x 8 x i64> [[_MSLD]], [[_MSLD1]] |
| 43 | +; CHECK-NEXT: [[TMP9:%.*]] = add <vscale x 8 x i64> [[TMP1]], [[TMP5]] |
| 44 | +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 |
| 45 | +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 87960930222080 |
| 46 | +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr |
| 47 | +; CHECK-NEXT: store <vscale x 8 x i64> [[_MSLD1]], ptr [[TMP12]], align 64 |
| 48 | +; CHECK-NEXT: store <vscale x 8 x i64> [[TMP5]], ptr [[B]], align 64 |
| 49 | +; CHECK-NEXT: ret void |
| 50 | +; |
| 51 | + %1 = load <vscale x 8 x i64>, ptr %a |
| 52 | + %2 = load <vscale x 8 x i64>, ptr %b |
| 53 | + %3 = add <vscale x 8 x i64> %1, %2 |
| 54 | + store <vscale x 8 x i64> %2, ptr %b |
| 55 | + ret void |
| 56 | +} |
| 57 | + |
| 58 | +define void @test_load_store_float(ptr %a, ptr %b) sanitize_memory { |
| 59 | +; CHECK-LABEL: define void @test_load_store_float( |
| 60 | +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { |
| 61 | +; CHECK-NEXT: call void @llvm.donothing() |
| 62 | +; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 4 x float>, ptr [[A]], align 16 |
| 63 | +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 |
| 64 | +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 |
| 65 | +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr |
| 66 | +; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 16 |
| 67 | +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64 |
| 68 | +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 |
| 69 | +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr |
| 70 | +; CHECK-NEXT: store <vscale x 4 x i32> [[_MSLD]], ptr [[TMP7]], align 16 |
| 71 | +; CHECK-NEXT: store <vscale x 4 x float> [[TMP1]], ptr [[B]], align 16 |
| 72 | +; CHECK-NEXT: ret void |
| 73 | +; |
| 74 | + %1 = load <vscale x 4 x float>, ptr %a |
| 75 | + store <vscale x 4 x float> %1, ptr %b |
| 76 | + ret void |
| 77 | +} |
| 78 | + |
| 79 | +define void @test_load_store_add_float(ptr %a, ptr %b) sanitize_memory { |
| 80 | +; CHECK-LABEL: define void @test_load_store_add_float( |
| 81 | +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { |
| 82 | +; CHECK-NEXT: call void @llvm.donothing() |
| 83 | +; CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 2 x float>, ptr [[A]], align 8 |
| 84 | +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 |
| 85 | +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 |
| 86 | +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr |
| 87 | +; CHECK-NEXT: [[_MSLD:%.*]] = load <vscale x 2 x i32>, ptr [[TMP4]], align 8 |
| 88 | +; CHECK-NEXT: [[TMP5:%.*]] = load <vscale x 2 x float>, ptr [[B]], align 8 |
| 89 | +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[B]] to i64 |
| 90 | +; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080 |
| 91 | +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr |
| 92 | +; CHECK-NEXT: [[_MSLD1:%.*]] = load <vscale x 2 x i32>, ptr [[TMP8]], align 8 |
| 93 | +; CHECK-NEXT: [[_MSPROP:%.*]] = or <vscale x 2 x i32> [[_MSLD]], [[_MSLD1]] |
| 94 | +; CHECK-NEXT: [[TMP9:%.*]] = fadd <vscale x 2 x float> [[TMP1]], [[TMP5]] |
| 95 | +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 |
| 96 | +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 87960930222080 |
| 97 | +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr |
| 98 | +; CHECK-NEXT: store <vscale x 2 x i32> [[_MSLD1]], ptr [[TMP12]], align 8 |
| 99 | +; CHECK-NEXT: store <vscale x 2 x float> [[TMP5]], ptr [[B]], align 8 |
| 100 | +; CHECK-NEXT: ret void |
| 101 | +; |
| 102 | + %1 = load <vscale x 2 x float>, ptr %a |
| 103 | + %2 = load <vscale x 2 x float>, ptr %b |
| 104 | + %3 = fadd <vscale x 2 x float> %1, %2 |
| 105 | + store <vscale x 2 x float> %2, ptr %b |
| 106 | + ret void |
| 107 | +} |
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