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[ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1
Summary: Add support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1. Neoverse E1 and Cortex-A65(&AE) only implement the AArch64 state of the Arm architecture. Neoverse N1 implements both AArch32 and AArch64. Cortex-A65: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65 Cortex-A65AE: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae Neoverse E1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-e1 Neoverse N1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1 Patch by Diogo Sampaio and Pablo Barrio Reviewers: samparker, LukeCheeseman, sbaranga, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64406 llvm-svn: 367007
1 parent aeac909 commit 2759545

19 files changed

+164
-16
lines changed

‎llvm/include/llvm/Support/AArch64TargetParser.def

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,12 @@ AARCH64_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
9292
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC))
9393
AARCH64_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
9494
(AArch64::AEK_CRC))
95+
AARCH64_CPU_NAME("cortex-a65", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
96+
(AArch64::AEK_DOTPROD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
97+
AArch64::AEK_RCPC | AArch64::AEK_SSBS))
98+
AARCH64_CPU_NAME("cortex-a65ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
99+
(AArch64::AEK_DOTPROD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
100+
AArch64::AEK_RCPC | AArch64::AEK_SSBS))
95101
AARCH64_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
96102
(AArch64::AEK_CRC))
97103
AARCH64_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
@@ -104,6 +110,13 @@ AARCH64_CPU_NAME("cortex-a76", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
104110
AARCH64_CPU_NAME("cortex-a76ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
105111
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
106112
AArch64::AEK_SSBS))
113+
AARCH64_CPU_NAME("neoverse-e1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
114+
(AArch64::AEK_DOTPROD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
115+
AArch64::AEK_RCPC | AArch64::AEK_SSBS))
116+
AARCH64_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
117+
(AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
118+
AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_RCPC |
119+
AArch64::AEK_SSBS))
107120
AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
108121
(AArch64::AEK_NONE))
109122
AARCH64_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,

‎llvm/include/llvm/Support/ARMTargetParser.def

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,8 @@ ARM_CPU_NAME("cortex-a76", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
274274
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
275275
ARM_CPU_NAME("cortex-a76ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
276276
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
277+
ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
278+
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
277279
ARM_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
278280
ARM_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
279281
ARM_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 45 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -354,7 +354,7 @@ def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
354354
FeaturePAN, FeatureLOR, FeatureVH]>;
355355

356356
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
357-
"Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
357+
"Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
358358
FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
359359

360360
def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
@@ -484,6 +484,19 @@ def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
484484
FeaturePredictableSelectIsExpensive
485485
]>;
486486

487+
def ProcA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
488+
"Cortex-A65 ARM processors", [
489+
HasV8_2aOps,
490+
FeatureCrypto,
491+
FeatureDotProd,
492+
FeatureFPARMv8,
493+
FeatureFullFP16,
494+
FeatureNEON,
495+
FeatureRAS,
496+
FeatureRCPC,
497+
FeatureSSBS,
498+
]>;
499+
487500
def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
488501
"Cortex-A72 ARM processors", [
489502
FeatureCRC,
@@ -641,6 +654,33 @@ def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
641654
FeatureSlowSTRQro
642655
]>;
643656

657+
def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
658+
"NeoverseE1",
659+
"Neoverse E1 ARM processors", [
660+
HasV8_2aOps,
661+
FeatureCrypto,
662+
FeatureDotProd,
663+
FeatureFPARMv8,
664+
FeatureFullFP16,
665+
FeatureNEON,
666+
FeatureRCPC,
667+
FeatureSSBS,
668+
]>;
669+
670+
def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
671+
"NeoverseN1",
672+
"Neoverse N1 ARM processors", [
673+
HasV8_2aOps,
674+
FeatureCrypto,
675+
FeatureDotProd,
676+
FeatureFPARMv8,
677+
FeatureFullFP16,
678+
FeatureNEON,
679+
FeatureRCPC,
680+
FeatureSPE,
681+
FeatureSSBS,
682+
]>;
683+
644684
def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
645685
"Qualcomm Saphira processors", [
646686
FeatureCrypto,
@@ -735,16 +775,19 @@ def : ProcessorModel<"generic", NoSchedModel, [
735775
FeaturePostRAScheduler
736776
]>;
737777

738-
// FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53.
739778
def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
740779
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
741780
def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
742781
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
782+
def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
783+
def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
743784
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
744785
def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
745786
def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
746787
def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
747788
def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
789+
def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
790+
def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
748791
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
749792
def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
750793
def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,8 @@ void AArch64Subtarget::initializeProperties() {
7979
MaxInterleaveFactor = 4;
8080
PrefFunctionAlignment = 4;
8181
break;
82+
case CortexA65:
83+
break;
8284
case CortexA72:
8385
case CortexA73:
8486
case CortexA75:
@@ -122,6 +124,9 @@ void AArch64Subtarget::initializeProperties() {
122124
// FIXME: remove this to enable 64-bit SLP if performance looks good.
123125
MinVectorRegisterBitWidth = 128;
124126
break;
127+
case NeoverseE1:
128+
case NeoverseN1:
129+
break;
125130
case Saphira:
126131
MaxInterleaveFactor = 4;
127132
// FIXME: remove this to enable 64-bit SLP if performance looks good.

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
4242
CortexA53,
4343
CortexA55,
4444
CortexA57,
45+
CortexA65,
4546
CortexA72,
4647
CortexA73,
4748
CortexA75,
@@ -51,6 +52,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
5152
ExynosM3,
5253
Falkor,
5354
Kryo,
55+
NeoverseE1,
56+
NeoverseN1,
5457
Saphira,
5558
ThunderX2T99,
5659
ThunderX,

‎llvm/lib/Target/ARM/ARM.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1156,6 +1156,13 @@ def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76,
11561156
FeatureFullFP16,
11571157
FeatureDotProd]>;
11581158

1159+
def : ProcNoItin<"neoverse-n1", [ARMv82a,
1160+
FeatureHWDivThumb,
1161+
FeatureHWDivARM,
1162+
FeatureCrypto,
1163+
FeatureCRC,
1164+
FeatureDotProd]>;
1165+
11591166
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
11601167
FeatureHasRetAddrStack,
11611168
FeatureNEONForFP,

‎llvm/lib/Target/ARM/ARMSubtarget.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -303,6 +303,8 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
303303
case Krait:
304304
PreISelOperandLatencyAdjustment = 1;
305305
break;
306+
case NeoverseN1:
307+
break;
306308
case Swift:
307309
MaxInterleaveFactor = 2;
308310
LdStMultipleTiming = SingleIssuePlusExtras;

‎llvm/lib/Target/ARM/ARMSubtarget.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
7171
Exynos,
7272
Krait,
7373
Kryo,
74+
NeoverseN1,
7475
Swift
7576
};
7677
enum ARMProcClassEnum {

‎llvm/test/CodeGen/AArch64/cpus.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,15 @@
66
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
77
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a55 2>&1 | FileCheck %s
88
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
9+
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a65 2>&1 | FileCheck %s
10+
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a65ae 2>&1 | FileCheck %s
911
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s
1012
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 | FileCheck %s
1113
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a75 2>&1 | FileCheck %s
1214
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a76ae 2>&1 | FileCheck %s
1315
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a76 2>&1 | FileCheck %s
16+
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
17+
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
1418
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 | FileCheck %s
1519
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m2 2>&1 | FileCheck %s
1620
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s

‎llvm/test/CodeGen/AArch64/neon-dot-product.ll

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,8 @@
1-
; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
1+
; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
2+
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=cortex-a65 < %s | FileCheck %s
3+
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=cortex-a65ae < %s | FileCheck %s
4+
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-e1 < %s | FileCheck %s
5+
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n1 < %s | FileCheck %s
26

37
declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
48
declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)

‎llvm/test/CodeGen/AArch64/remat.ll

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,13 @@
22
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
33
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s | FileCheck %s
44
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
5+
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a65 -o - %s | FileCheck %s
6+
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a65ae -o - %s | FileCheck %s
57
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
68
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s | FileCheck %s
79
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a75 -o - %s | FileCheck %s
10+
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=neoverse-e1 -o - %s | FileCheck %s
11+
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=neoverse-n1 -o - %s | FileCheck %s
812
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s | FileCheck %s
913
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m2 -o - %s | FileCheck %s
1014
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s | FileCheck %s
@@ -26,9 +30,9 @@ entry:
2630
; CHECK: add x0, sp, #8
2731
; CHECK-NOT: mov
2832
; CHECK-NEXT: bl f
29-
call void @f(%X* %tmp)
33+
call void @f(%X* %tmp)
3034
; CHECK: add x0, sp, #8
3135
; CHECK-NOT: mov
3236
; CHECK-NEXT: bl f
33-
ret void
37+
ret void
3438
}

‎llvm/test/MC/AArch64/armv8.2a-dotprod.s

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,23 @@
11
// RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
2+
// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
3+
// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a65 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
4+
// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a65ae -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
25
// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
36
// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a76 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
4-
// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
7+
// RUN: llvm-mc -triple aarch64 -mcpu=neoverse-e1 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
8+
// RUN: llvm-mc -triple aarch64 -mcpu=neoverse-n1 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD
59
// RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
10+
611
// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
712
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
13+
// RUN: not llvm-mc -triple aarch64 -mcpu=cortex-a65 -mattr=-dotprod -show-encoding < %s 2> %t
14+
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
15+
// RUN: not llvm-mc -triple aarch64 -mcpu=cortex-a65ae -mattr=-dotprod -show-encoding < %s 2> %t
16+
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
17+
// RUN: not llvm-mc -triple aarch64 -mcpu=neoverse-e1 -mattr=-dotprod -show-encoding < %s 2> %t
18+
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
19+
// RUN: not llvm-mc -triple aarch64 -mcpu=neoverse-n1 -mattr=-dotprod -show-encoding < %s 2> %t
20+
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
821

922
udot v0.2s, v1.8b, v2.8b
1023
sdot v0.2s, v1.8b, v2.8b

‎llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe < %s | FileCheck %s
2+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s | FileCheck %s
23
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=NO_SPE %s
34

45
psb csync

‎llvm/test/MC/AArch64/armv8.3a-rcpc.s

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,10 @@
11
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
2+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a65 < %s 2>&1 | FileCheck %s
3+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a65ae < %s 2>&1 | FileCheck %s
24
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s 2>&1 | FileCheck %s
35
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s 2>&1 | FileCheck %s
6+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-e1 < %s 2>&1 | FileCheck %s
7+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s
48
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
59
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
610
// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t

‎llvm/test/MC/AArch64/armv8.5a-ssbs.s

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
11
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s | FileCheck %s
22
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
3-
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76 < %s | FileCheck %s
4-
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76ae < %s | FileCheck %s
3+
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65 < %s | FileCheck %s
4+
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a65ae < %s | FileCheck %s
5+
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76 < %s | FileCheck %s
6+
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76ae < %s | FileCheck %s
7+
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=neoverse-e1 < %s | FileCheck %s
8+
// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=neoverse-n1 < %s | FileCheck %s
59
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
610

711
mrs x2, SSBS

‎llvm/test/MC/ARM/armv8.2a-dotprod-a32.s

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
// RUN: llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK
2+
// RUN: llvm-mc -triple arm -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
23
// RUN: llvm-mc -triple arm -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
34
// RUN: llvm-mc -triple arm -mcpu=cortex-a76 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
4-
// RUN: llvm-mc -triple arm -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
5+
// RUN: llvm-mc -triple arm -mcpu=neoverse-n1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
56

67
// RUN: not llvm-mc -triple arm -mattr=-dotprod -show-encoding < %s 2> %t
78
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s

‎llvm/test/MC/ARM/armv8.2a-dotprod-t32.s

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
// RUN: llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK
2+
// RUN: llvm-mc -triple thumb -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
23
// RUN: llvm-mc -triple thumb -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
34
// RUN: llvm-mc -triple thumb -mcpu=cortex-a76 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
4-
// RUN: llvm-mc -triple thumb -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
5+
// RUN: llvm-mc -triple thumb -mcpu=neoverse-n1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
56

67
// RUN: not llvm-mc -triple thumb -mattr=-dotprod -show-encoding < %s 2> %t
78
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s

‎llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
1+
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a -mattr=+rcpc --disassemble < %s | FileCheck %s
12
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
2-
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 --disassemble < %s | FileCheck %s
33
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 --disassemble < %s | FileCheck %s
4-
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a -mattr=+rcpc --disassemble < %s | FileCheck %s
4+
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a65 --disassemble < %s | FileCheck %s
5+
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a65ae --disassemble < %s | FileCheck %s
6+
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 --disassemble < %s | FileCheck %s
7+
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s
8+
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s
59

610
# CHECK: ldaprb w0, [x0]
711
# CHECK: ldaprh w0, [x0]
@@ -26,4 +30,3 @@
2630
# CHECK-V8_2A: warning: invalid instruction encoding
2731
# CHECK-V8_2A: [0x00,0xc0,0xbf,0xf8]
2832
# CHECK-V8_2A: ^
29-

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