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Merge commit '9c5ebf035896' from llvm.org/main into apple/main
2 parents 818915c + 9c5ebf0 commit 2daf798

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‎llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll

Lines changed: 51 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
12
; RUN: opt -S -o - -basic-aa -domtree -gvn %s | FileCheck %s
23

34
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
@@ -10,13 +11,35 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
1011

1112
; Check that GVN doesn't determine %2 is partially redundant.
1213

13-
; CHECK-LABEL: define i32 @volatile_load
14-
; CHECK: for.body:
15-
; CHECK: %2 = load i32, i32*
16-
; CHECK: %3 = load volatile i32, i32*
17-
; CHECK: for.cond.for.end_crit_edge:
18-
1914
define i32 @volatile_load(i32 %n) {
15+
; CHECK-LABEL: @volatile_load(
16+
; CHECK-NEXT: entry:
17+
; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
18+
; CHECK-NEXT: br i1 [[CMP6]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]]
19+
; CHECK: for.body.lr.ph:
20+
; CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** @a2, align 8, !tbaa [[TBAA5:![0-9]+]]
21+
; CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @a, align 8, !tbaa [[TBAA5]]
22+
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
23+
; CHECK: for.body:
24+
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
25+
; CHECK-NEXT: [[S_09:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
26+
; CHECK-NEXT: [[P_08:%.*]] = phi i32* [ [[TMP0]], [[FOR_BODY_LR_PH]] ], [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ]
27+
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[P_08]], align 4, !tbaa [[TBAA9:![0-9]+]]
28+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[INDVARS_IV]]
29+
; CHECK-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4, !tbaa [[TBAA9]]
30+
; CHECK-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[P_08]], align 4, !tbaa [[TBAA9]]
31+
; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP3]], [[S_09]]
32+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
33+
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i32, i32* [[P_08]], i64 1
34+
; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
35+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[N]]
36+
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]]
37+
; CHECK: for.cond.for.end_crit_edge:
38+
; CHECK-NEXT: br label [[FOR_END]]
39+
; CHECK: for.end:
40+
; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_COND_FOR_END_CRIT_EDGE]] ], [ 0, [[ENTRY:%.*]] ]
41+
; CHECK-NEXT: ret i32 [[S_0_LCSSA]]
42+
;
2043
entry:
2144
%cmp6 = icmp sgt i32 %n, 0
2245
br i1 %cmp6, label %for.body.lr.ph, label %for.end
@@ -53,16 +76,26 @@ for.end:
5376
; %1 is partially redundant if %0 can be widened to a 64-bit load.
5477
; But we should not widen %0 to 64-bit load.
5578

56-
; CHECK-LABEL: define i32 @overaligned_load
57-
; CHECK: if.then:
58-
; CHECK-NOT: %0 = load i64
59-
; CHECK-NOT: [[LSHR:%[0-9]+]] = lshr i64 %0, 32, !dbg [[LSHR_LOC:![0-9]+]]
60-
; CHECK-NOT: trunc i64 [[LSHR]] to i32
61-
; CHECK: if.end:
62-
; CHECK: %1 = load i32, i32*
63-
; CHECK-NOT: [[LSHR_LOC]] = !DILocation(line: 101, column: 1, scope: !{{.*}})
64-
6579
define i32 @overaligned_load(i32 %a, i32* nocapture %b) !dbg !13 {
80+
; CHECK-LABEL: @overaligned_load(
81+
; CHECK-NEXT: entry:
82+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A:%.*]], 0, !dbg [[DBG14:![0-9]+]]
83+
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !dbg [[DBG14]]
84+
; CHECK: if.then:
85+
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @s1, i64 0, i32 0), align 8, !dbg [[DBG15:![0-9]+]], !tbaa [[TBAA9]]
86+
; CHECK-NEXT: br label [[IF_END:%.*]], !dbg [[DBG15]]
87+
; CHECK: if.else:
88+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 2, !dbg [[DBG16:![0-9]+]]
89+
; CHECK-NEXT: store i32 10, i32* [[ARRAYIDX]], align 4, !dbg [[DBG16]], !tbaa [[TBAA9]]
90+
; CHECK-NEXT: br label [[IF_END]], !dbg [[DBG16]]
91+
; CHECK: if.end:
92+
; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN]] ], [ 0, [[IF_ELSE]] ]
93+
; CHECK-NEXT: [[P_0:%.*]] = phi i32* [ getelementptr inbounds ([[STRUCT_S1]], %struct.S1* @s1, i64 0, i32 0), [[IF_THEN]] ], [ [[B]], [[IF_ELSE]] ]
94+
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[P_0]], i64 1, !dbg [[DBG17:![0-9]+]]
95+
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ADD_PTR]], align 4, !dbg [[DBG17]], !tbaa [[TBAA9]]
96+
; CHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], [[I_0]], !dbg [[DBG17]]
97+
; CHECK-NEXT: ret i32 [[ADD1]], !dbg [[DBG17]]
98+
;
6699
entry:
67100
%cmp = icmp sgt i32 %a, 0, !dbg !14
68101
br i1 %cmp, label %if.then, label %if.else, !dbg !14
@@ -107,6 +140,6 @@ if.end:
107140
!16 = !DILocation(line: 102, column: 1, scope: !13)
108141
!17 = !DILocation(line: 103, column: 1, scope: !13)
109142
!18 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang",
110-
file: !12,
111-
isOptimized: true, flags: "-O2",
112-
splitDebugFilename: "abc.debug", emissionKind: 2)
143+
file: !12,
144+
isOptimized: true, flags: "-O2",
145+
splitDebugFilename: "abc.debug", emissionKind: 2)

‎llvm/test/Transforms/GVN/big-endian.ll

Lines changed: 26 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,29 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
12
; RUN: opt -gvn -S < %s | FileCheck %s
23

3-
target datalayout = "E-m:e-i64:64-n32:64"
4-
target triple = "powerpc64-unknown-linux-gnu"
4+
target datalayout = "E-m:e-i64:64-n32:64"
5+
target triple = "powerpc64-unknown-linux-gnu"
56

67
;; Make sure we use correct bit shift based on storage size for
78
;; loads reusing a load value.
89
define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
9-
; CHECK-LABEL: @test1
10-
; CHECK-NOT: [[V1:%.*]] = load i16, i16* %{{.*}}
11-
; CHECK-NOT: [[V2:%.*]] = lshr i16 [[V1]], 8
12-
; CHECK-NOT: trunc i16 [[V2]] to i1
10+
; CHECK-LABEL: @test1(
11+
; CHECK-NEXT: [[VALUELOADA_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA:%.*]], i64 0, i32 0
12+
; CHECK-NEXT: [[VALUELOADA_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADA_FCA_0_GEP]], align 8
13+
; CHECK-NEXT: [[VALUELOADB_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB:%.*]], i64 0, i32 0
14+
; CHECK-NEXT: [[VALUELOADB_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADB_FCA_0_GEP]], align 8
15+
; CHECK-NEXT: [[ISTRUE:%.*]] = and i1 [[VALUELOADA_FCA_0_LOAD]], [[VALUELOADB_FCA_0_LOAD]]
16+
; CHECK-NEXT: [[VALUELOADA_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA]], i64 0, i32 1
17+
; CHECK-NEXT: [[VALUELOADA_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADA_FCA_1_GEP]], align 1
18+
; CHECK-NEXT: [[ISNOTNULLA:%.*]] = icmp ne i8 [[VALUELOADA_FCA_1_LOAD]], 0
19+
; CHECK-NEXT: [[VALUELOADB_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB]], i64 0, i32 1
20+
; CHECK-NEXT: [[VALUELOADB_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADB_FCA_1_GEP]], align 1
21+
; CHECK-NEXT: [[ISNOTNULLB:%.*]] = icmp ne i8 [[VALUELOADB_FCA_1_LOAD]], 0
22+
; CHECK-NEXT: [[ISNOTNULL:%.*]] = and i1 [[ISNOTNULLA]], [[ISNOTNULLB]]
23+
; CHECK-NEXT: [[ISTRUEANDNOTNULL:%.*]] = and i1 [[ISTRUE]], [[ISNOTNULL]]
24+
; CHECK-NEXT: [[RET:%.*]] = zext i1 [[ISTRUEANDNOTNULL]] to i64
25+
; CHECK-NEXT: ret i64 [[RET]]
26+
;
1327

1428
%valueLoadA.fca.0.gep = getelementptr inbounds { i1, i8 }, { i1, i8 }* %predA, i64 0, i32 0
1529
%valueLoadA.fca.0.load = load i1, i1* %valueLoadA.fca.0.gep, align 8
@@ -30,8 +44,12 @@ define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
3044

3145
;; And likewise for loads reusing a store value.
3246
define i1 @test2(i8 %V, i8* %P) {
33-
; CHECK-LABEL: @test2
34-
; CHECK-NOT: lshr
47+
; CHECK-LABEL: @test2(
48+
; CHECK-NEXT: store i8 [[V:%.*]], i8* [[P:%.*]], align 1
49+
; CHECK-NEXT: [[P2:%.*]] = bitcast i8* [[P]] to i1*
50+
; CHECK-NEXT: [[TMP1:%.*]] = trunc i8 [[V]] to i1
51+
; CHECK-NEXT: ret i1 [[TMP1]]
52+
;
3553
store i8 %V, i8* %P
3654
%P2 = bitcast i8* %P to i1*
3755
%A = load i1, i1* %P2

‎llvm/test/Transforms/NewGVN/big-endian.ll

Lines changed: 26 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,29 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
12
; RUN: opt -newgvn -S < %s | FileCheck %s
23

3-
target datalayout = "E-m:e-i64:64-n32:64"
4-
target triple = "powerpc64-unknown-linux-gnu"
4+
target datalayout = "E-m:e-i64:64-n32:64"
5+
target triple = "powerpc64-unknown-linux-gnu"
56

67
;; Make sure we use correct bit shift based on storage size for
78
;; loads reusing a load value.
89
define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
9-
; CHECK-LABEL: @test1
10-
; CHECK-NOT: [[V1:%.*]] = load i16, i16* %{{.*}}
11-
; CHECK-NOT: [[V2:%.*]] = lshr i16 [[V1]], 8
12-
; CHECK-NOT: trunc i16 [[V2]] to i1
10+
; CHECK-LABEL: @test1(
11+
; CHECK-NEXT: [[VALUELOADA_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA:%.*]], i64 0, i32 0
12+
; CHECK-NEXT: [[VALUELOADA_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADA_FCA_0_GEP]], align 8
13+
; CHECK-NEXT: [[VALUELOADB_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB:%.*]], i64 0, i32 0
14+
; CHECK-NEXT: [[VALUELOADB_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADB_FCA_0_GEP]], align 8
15+
; CHECK-NEXT: [[ISTRUE:%.*]] = and i1 [[VALUELOADA_FCA_0_LOAD]], [[VALUELOADB_FCA_0_LOAD]]
16+
; CHECK-NEXT: [[VALUELOADA_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA]], i64 0, i32 1
17+
; CHECK-NEXT: [[VALUELOADA_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADA_FCA_1_GEP]], align 1
18+
; CHECK-NEXT: [[ISNOTNULLA:%.*]] = icmp ne i8 [[VALUELOADA_FCA_1_LOAD]], 0
19+
; CHECK-NEXT: [[VALUELOADB_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB]], i64 0, i32 1
20+
; CHECK-NEXT: [[VALUELOADB_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADB_FCA_1_GEP]], align 1
21+
; CHECK-NEXT: [[ISNOTNULLB:%.*]] = icmp ne i8 [[VALUELOADB_FCA_1_LOAD]], 0
22+
; CHECK-NEXT: [[ISNOTNULL:%.*]] = and i1 [[ISNOTNULLA]], [[ISNOTNULLB]]
23+
; CHECK-NEXT: [[ISTRUEANDNOTNULL:%.*]] = and i1 [[ISTRUE]], [[ISNOTNULL]]
24+
; CHECK-NEXT: [[RET:%.*]] = zext i1 [[ISTRUEANDNOTNULL]] to i64
25+
; CHECK-NEXT: ret i64 [[RET]]
26+
;
1327

1428
%valueLoadA.fca.0.gep = getelementptr inbounds { i1, i8 }, { i1, i8 }* %predA, i64 0, i32 0
1529
%valueLoadA.fca.0.load = load i1, i1* %valueLoadA.fca.0.gep, align 8
@@ -30,8 +44,12 @@ define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
3044

3145
;; And likewise for loads reusing a store value.
3246
define i1 @test2(i8 %V, i8* %P) {
33-
; CHECK-LABEL: @test2
34-
; CHECK-NOT: lshr
47+
; CHECK-LABEL: @test2(
48+
; CHECK-NEXT: store i8 [[V:%.*]], i8* [[P:%.*]], align 1
49+
; CHECK-NEXT: [[P2:%.*]] = bitcast i8* [[P]] to i1*
50+
; CHECK-NEXT: [[A:%.*]] = load i1, i1* [[P2]], align 1
51+
; CHECK-NEXT: ret i1 [[A]]
52+
;
3553
store i8 %V, i8* %P
3654
%P2 = bitcast i8* %P to i1*
3755
%A = load i1, i1* %P2

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