[InstSimplify] Test case for D149001 (NFC)

Differential Revision: https://reviews.llvm.org/D149012

Author: floatshadow

llvm/test/Transforms/InstSimplify/div.ll

@@ -434,3 +434,161 @@ define <2 x i8> @udiv_exact_trailing_zeros_nonuniform_vector(<2 x i8> %x) {
 }
 
 !0 = !{i32 0, i32 3}
+
+define i32 @sdiv_one_srem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @sdiv_one_srem_divisor(
+; CHECK-NEXT:    [[SREM:%.*]] = srem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[SDIV:%.*]] = sdiv i32 [[A:%.*]], [[SREM]]
+; CHECK-NEXT:    ret i32 [[SDIV]]
+;
+  %srem = srem i32 1, %b
+  %sdiv = sdiv i32 %a, %srem
+  ret i32 %sdiv
+}
+
+define i32 @sdiv_one_urem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @sdiv_one_urem_divisor(
+; CHECK-NEXT:    [[UREM:%.*]] = urem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[SDIV:%.*]] = sdiv i32 [[A:%.*]], [[UREM]]
+; CHECK-NEXT:    ret i32 [[SDIV]]
+;
+  %urem = urem i32 1, %b
+  %sdiv = sdiv i32 %a, %urem
+  ret i32 %sdiv
+}
+
+define i32 @udiv_one_srem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @udiv_one_srem_divisor(
+; CHECK-NEXT:    [[SREM:%.*]] = srem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[UDIV:%.*]] = udiv i32 [[A:%.*]], [[SREM]]
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %srem = srem i32 1, %b
+  %udiv = udiv i32 %a, %srem
+  ret i32 %udiv
+}
+
+define i32 @udiv_one_urem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @udiv_one_urem_divisor(
+; CHECK-NEXT:    [[UREM:%.*]] = urem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[UDIV:%.*]] = udiv i32 [[A:%.*]], [[UREM]]
+; CHECK-NEXT:    ret i32 [[UDIV]]
+;
+  %urem = urem i32 1, %b
+  %udiv = udiv i32 %a, %urem
+  ret i32 %udiv
+}
+
+define i32 @srem_one_srem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @srem_one_srem_divisor(
+; CHECK-NEXT:    [[SREM:%.*]] = srem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[SREM1:%.*]] = srem i32 [[A:%.*]], [[SREM]]
+; CHECK-NEXT:    ret i32 [[SREM1]]
+;
+  %srem = srem i32 1, %b
+  %srem1 = srem i32 %a, %srem
+  ret i32 %srem1
+}
+
+define i32 @urem_one_srem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @urem_one_srem_divisor(
+; CHECK-NEXT:    [[SREM:%.*]] = srem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[UREM:%.*]] = urem i32 [[A:%.*]], [[SREM]]
+; CHECK-NEXT:    ret i32 [[UREM]]
+;
+  %srem = srem i32 1, %b
+  %urem = urem i32 %a, %srem
+  ret i32 %urem
+}
+
+define i32 @srem_one_urem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @srem_one_urem_divisor(
+; CHECK-NEXT:    [[UREM:%.*]] = urem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[SREM:%.*]] = srem i32 [[A:%.*]], [[UREM]]
+; CHECK-NEXT:    ret i32 [[SREM]]
+;
+  %urem = urem i32 1, %b
+  %srem = srem i32 %a, %urem
+  ret i32 %srem
+}
+
+define i32 @urem_one_urem_divisor(i32 %a, i32 %b) {
+; CHECK-LABEL: @urem_one_urem_divisor(
+; CHECK-NEXT:    [[UREM:%.*]] = urem i32 1, [[B:%.*]]
+; CHECK-NEXT:    [[UREM1:%.*]] = urem i32 [[A:%.*]], [[UREM]]
+; CHECK-NEXT:    ret i32 [[UREM1]]
+;
+  %urem = urem i32 1, %b
+  %urem1 = urem i32 %a, %urem
+  ret i32 %urem1
+}
+
+define <2 x i8> @sdiv_one_vec_srem_divisor(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @sdiv_one_vec_srem_divisor(
+; CHECK-NEXT:    [[SREM:%.*]] = srem <2 x i8> <i8 1, i8 1>, [[B:%.*]]
+; CHECK-NEXT:    [[SDIV:%.*]] = sdiv <2 x i8> [[A:%.*]], [[SREM]]
+; CHECK-NEXT:    ret <2 x i8> [[SDIV]]
+;
+  %srem = srem <2 x i8> <i8 1, i8 1>, %b
+  %sdiv = sdiv <2 x i8> %a, %srem
+  ret <2 x i8> %sdiv
+}
+
+define i32 @sdiv_and_one_divisor(i32 %x, i32 %y) {
+; CHECK-LABEL: @sdiv_and_one_divisor(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[RES:%.*]] = sdiv i32 [[Y:%.*]], [[AND]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %and = and i32 %x, 1
+  %res = sdiv i32 %y, %and
+  ret i32 %res
+}
+
+define <2 x i8> @sdiv_and_one_vec_divisor(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @sdiv_and_one_vec_divisor(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 1, i8 1>
+; CHECK-NEXT:    [[RES:%.*]] = sdiv <2 x i8> [[Y:%.*]], [[AND]]
+; CHECK-NEXT:    ret <2 x i8> [[RES]]
+;
+  %and = and <2 x i8> %x, <i8 1, i8 1>
+  %res = sdiv <2 x i8> %y, %and
+  ret <2 x i8> %res
+}
+
+define i32 @sdiv_neg_or_divisor(i32 %x, i32 %y) {
+; CHECK-LABEL: @sdiv_neg_or_divisor(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2
+; CHECK-NEXT:    [[NEG:%.*]] = xor i32 [[OR]], -1
+; CHECK-NEXT:    [[RES:%.*]] = sdiv i32 [[Y:%.*]], [[NEG]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %or = or i32 %x, -2
+  %neg = xor i32 %or, -1
+  %res = sdiv i32 %y, %neg
+  ret i32 %res
+}
+
+define i32 @sdiv_neg_or_multi_one_bit_divisor(i32 %x, i32 %y) {
+; CHECK-LABEL: @sdiv_neg_or_multi_one_bit_divisor(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -3
+; CHECK-NEXT:    [[NEG:%.*]] = xor i32 [[OR]], -1
+; CHECK-NEXT:    [[RES:%.*]] = sdiv i32 [[Y:%.*]], [[NEG]]
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %or = or i32 %x, -3
+  %neg = xor i32 %or, -1
+  %res = sdiv i32 %y, %neg
+  ret i32 %res
+}
+
+define <2 x i8> @sdiv_vec_multi_one_bit_divisor(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @sdiv_vec_multi_one_bit_divisor(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 1, i8 3>
+; CHECK-NEXT:    [[RES:%.*]] = sdiv <2 x i8> [[Y:%.*]], [[AND]]
+; CHECK-NEXT:    ret <2 x i8> [[RES]]
+;
+  %and = and <2 x i8> %x, <i8 1, i8 3>
+  %res = sdiv <2 x i8> %y, %and
+  ret <2 x i8> %res
+}